Remove MOVSX immediate support

Signed-off-by: Dave Thaler <[email protected]>
vbpf · Feb 5, 2024 · 342996d · 342996d
1 parent 55478db
commit 342996d
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Showing 3 changed files with 11 additions and 68 deletions.
diff --git a/src/asm_unmarshal.cpp b/src/asm_unmarshal.cpp
@@ -110,6 +110,8 @@ struct Unmarshaller {
             default: throw InvalidInstruction(pc, make_opcode_message("invalid offset for", inst.opcode));
             }
         case INST_ALU_OP_MOV:
+            if (inst.offset > 0 && !(inst.opcode & INST_SRC_REG))
+                throw InvalidInstruction(pc, make_opcode_message("invalid offset for", inst.opcode));
             switch (inst.offset) {
             case 0: return Bin::Op::MOV;
             case 8: return Bin::Op::MOVSX8;

diff --git a/src/test/test_marshal.cpp b/src/test/test_marshal.cpp
@@ -88,16 +88,20 @@ static const auto ws = {1, 2, 4, 8};
 
 TEST_CASE("disasm_marshal", "[disasm][marshal]") {
     SECTION("Bin") {
-        auto ops = {Bin::Op::MOV, Bin::Op::ADD, Bin::Op::SUB, Bin::Op::MUL, Bin::Op::UDIV,  Bin::Op::UMOD,
-                    Bin::Op::OR,  Bin::Op::AND, Bin::Op::LSH, Bin::Op::RSH, Bin::Op::ARSH, Bin::Op::XOR,
-                    Bin::Op::SDIV, Bin::Op::SMOD, Bin::Op::MOVSX8, Bin::Op::MOVSX16, Bin::Op::MOVSX32};
         SECTION("Reg src") {
+            auto ops = {Bin::Op::MOV,  Bin::Op::ADD,  Bin::Op::SUB,    Bin::Op::MUL,     Bin::Op::UDIV,   Bin::Op::UMOD,
+                        Bin::Op::OR,   Bin::Op::AND,  Bin::Op::LSH,    Bin::Op::RSH,     Bin::Op::ARSH,   Bin::Op::XOR,
+                        Bin::Op::SDIV, Bin::Op::SMOD, Bin::Op::MOVSX8, Bin::Op::MOVSX16, Bin::Op::MOVSX32};
             for (auto op : ops) {
                 compare_marshal_unmarshal(Bin{.op = op, .dst = Reg{1}, .v = Reg{2}, .is64 = true});
                 compare_marshal_unmarshal(Bin{.op = op, .dst = Reg{1}, .v = Reg{2}, .is64 = false});
             }
         }
         SECTION("Imm src") {
+            // MOVSX* instructions are not defined for Imm, only Reg.
+            auto ops = {Bin::Op::MOV,  Bin::Op::ADD, Bin::Op::SUB,  Bin::Op::MUL, Bin::Op::UDIV,
+                        Bin::Op::UMOD, Bin::Op::OR,  Bin::Op::AND,  Bin::Op::LSH, Bin::Op::RSH,
+                        Bin::Op::ARSH, Bin::Op::XOR, Bin::Op::SDIV, Bin::Op::SMOD};
             for (auto op : ops) {
                 compare_marshal_unmarshal(Bin{.op = op, .dst = Reg{1}, .v = Imm{2}, .is64 = false});
                 compare_marshal_unmarshal(Bin{.op = op, .dst = Reg{1}, .v = Imm{2}, .is64 = true});
@@ -377,6 +381,8 @@ TEST_CASE("fail unmarshal misc", "[disasm][marshal]") {
                          "0: Bad register\n");
     check_unmarshal_fail(ebpf_inst{.opcode = /* 0xb4 */ (INST_ALU_OP_MOV | INST_SRC_IMM | INST_CLS_ALU), .dst = 11, .imm = 8},
                          "0: Bad register\n");
+    check_unmarshal_fail(ebpf_inst{.opcode = /* 0xb4 */ INST_ALU_OP_MOV | INST_SRC_IMM | INST_CLS_ALU, .offset = 8},
+                         "0: invalid offset for op 0xb4\n");
     check_unmarshal_fail(ebpf_inst{.opcode = /* 0xbc */ (INST_ALU_OP_MOV | INST_SRC_REG | INST_CLS_ALU), .dst = 1, .src = 11},
                          "0: Bad register\n");
     check_unmarshal_fail(ebpf_inst{.opcode = /* 0xd4 */ INST_ALU_OP_END | INST_END_LE | INST_CLS_ALU, .dst = 1, .imm = 8},

diff --git a/test-data/movsx.yaml b/test-data/movsx.yaml
@@ -1,71 +1,6 @@
 # Copyright (c) Prevail Verifier contributors.
 # SPDX-License-Identifier: MIT
 ---
-test-case: movsx8 immediate to 32 bits
-
-pre: []
-
-code:
-  <start>: |
-    w1 s8= 384 ; 0x180 -> 0xFFFFFF80
-
-post:
-  - r1.type=number
-  - r1.svalue=4294967168
-  - r1.uvalue=4294967168
----
-test-case: movsx16 immediate to 32 bits
-
-pre: []
-
-code:
-  <start>: |
-    w1 s16= 98304 ; 0x18000 -> 0xFFFF8000
-
-post:
-  - r1.type=number
-  - r1.svalue=4294934528
-  - r1.uvalue=4294934528
----
-test-case: movsx8 immediate to 64 bits
-
-pre: []
-
-code:
-  <start>: |
-    r1 s8= 384 ; 0x180 -> 0xFFFFFFFFFFFFFF80
-
-post:
-  - r1.type=number
-  - r1.svalue=-128
-  - r1.uvalue=18446744073709551488
----
-test-case: movsx16 immediate to 64 bits
-
-pre: []
-
-code:
-  <start>: |
-    r1 s16= 98304 ; 0x18000 -> 0xFFFFFFFFFFFF8000
-
-post:
-  - r1.type=number
-  - r1.svalue=-32768
-  - r1.uvalue=18446744073709518848
----
-test-case: movsx32 immediate to 64 bits
-
-pre: []
-
-code:
-  <start>: |
-    r1 s32= 2147483648 ; 0x80000000 -> 0xFFFFFFFF80000000
-
-post:
-  - r1.type=number
-  - r1.svalue=-2147483648
-  - r1.uvalue=18446744071562067968
----
 test-case: movsx8 register to 32 bits
 
 pre: ["r1.svalue=384", "r1.uvalue=384", "r1.type=number", "r1.svalue=r1.uvalue"]