Add dedicated zero-extension and sign-extension instructions #529
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Signed-off-by: Elazar Gershuni <[email protected]>
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Issue #523 is relevant where there are now BPF instructions for sign extension |
dthaler
reviewed
Sep 27, 2023
| @@ -60,6 +60,8 @@ static uint8_t imm(Un::Op op) { | |||
| case Op::LE32: return 32; | |||
| case Op::BE64: | |||
| case Op::LE64: return 64; | |||
| case Op::ZEXT32: | |||
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I don't think ZEXT needs a new instruction, the existing BPF_MOV | BPF_ALU (0xbc) should already do zero-extension.
dthaler
reviewed
Sep 28, 2023
Comment on lines
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| {"zext32", Un::Op::ZEXT32}, | ||
| {"sext32", Un::Op::SEXT32}, |
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there are multiple new signed extension instructions that are Bin ops (not Un ops), so I don't think there's any reason to add Un ops here.
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I think sext32 can now be done using the MOVSX instruction
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FYI, I just started working on an update to this PR that will reuse now-existing instructions. It may take me until next week as I'm out of town for half the week. |
Alan-Jowett
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Oct 15, 2024
When register R12 is used in an instruction requiring a ModRM byte, the semantics and encoding of the instruction are unique. The emit_modrm_and_displacement function did not handle this uniqueness properly. This patch modifies the function to handle the use of R12 correctly. Fixes vbpf#529 Signed-off-by: Will Hawkins <[email protected]>
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Fix #63, which should also help with issues described in #479.
Pairs of
rX = rX << 32; rX = rX >> 32are translated to a single zero-extension instruction (if the second instruction is RSH) or sign-extension instruction (if the second instruction is ARSH).The translation is done during unmarshalling, similarly to LDDW instructions.
Semantically, zext is NOP if the unsigned value fits in 32 bits, and sext is nop if the signed value fits in 32 bits.
Otherwise, fall back to handling of left+right shift (which does not maintain relational invariants).
It may be possible to be more precise, but I don't think we need it at this point.