Merge pull request #1237 from taichi-ishitani/fix_miss_formated_sv

Fix miss fomratted SV
veryl-lang · Feb 12, 2025 · 614457c · 614457c
2 parents d5ce0b2 + a3867d1
commit 614457c
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Showing 4 changed files with 30 additions and 15 deletions.
diff --git a/crates/emitter/src/emitter.rs b/crates/emitter/src/emitter.rs
@@ -920,6 +920,8 @@ impl Emitter {
                 .iter()
                 .any(|y| x.name() == y.identifier.identifier_token.token.text)
         });
+
+        let src_line = self.src_line;
         for (i, port) in unconnected_ports.enumerate() {
             if i >= 1 || !connected_ports.is_empty() {
                 self.str(",");
@@ -928,6 +930,7 @@ impl Emitter {
 
             let property = port.property();
             self.str(".");
+            self.clear_adjust_line();
             self.align_start(align_kind::IDENTIFIER);
             self.token(&port.token);
             self.align_finish(align_kind::IDENTIFIER);
@@ -939,6 +942,7 @@ impl Emitter {
             self.str(")");
         }
 
+        self.src_line = src_line;
         self.generic_map.pop();
     }
 

diff --git a/testcases/map/testcases/sv/73_port_default_value.sv.map b/testcases/map/testcases/sv/73_port_default_value.sv.map
diff --git a/testcases/sv/73_port_default_value.sv b/testcases/sv/73_port_default_value.sv
@@ -6,40 +6,46 @@ module veryl_testcase___Module73A__0 (
     input  logic i_a,
     input  logic i_b,
     input  logic i_c,
-    output logic o_d
+    output logic o_d,
+    output logic o_e
 );
     always_comb o_d = 0;
+    always_comb o_e = 0;
 endmodule
 module veryl_testcase___Module73A__1 (
     input  logic i_a,
     input  logic i_b,
     input  logic i_c,
-    output logic o_d
+    output logic o_d,
+    output logic o_e
 );
     always_comb o_d = 0;
+    always_comb o_e = 0;
 endmodule
 
 module veryl_testcase_Module73B;
+    logic _d;
+
     veryl_testcase___Module73A__0 u0 (
         .i_a (veryl_testcase_Package73::A),
         .i_b (0                          ),
         .i_c (0),
-        .o_d ( )
-    )
-    ;
+        .o_d (                           ),
+        .o_e ()
+    );
     veryl_testcase___Module73A__1 u1 (
         .i_a (veryl_testcase_Package73::A),
         .i_b (1                          ),
         .i_c (0),
-        .o_d ( )
-    )
-    ;
+        .o_d (                           ),
+        .o_e ()
+    );
     veryl_testcase___Module73A__1 u2 (
-        .i_a (0),
-        .i_b (0),
+        .i_a (0 ),
+        .i_b (0 ),
+        .o_d (_d),
         .i_c (0),
-        .o_d ( )
-
+        .o_e ()
     );
 endmodule
 //# sourceMappingURL=../map/testcases/sv/73_port_default_value.sv.map
diff --git a/testcases/veryl/73_port_default_value.veryl b/testcases/veryl/73_port_default_value.veryl
@@ -7,15 +7,20 @@ module Module73A::<B: const> (
     i_b: input  logic = B           ,
     i_c: input  logic = 0           ,
     o_d: output logic = _           ,
+    o_e: output logic = _           ,
 ) {
     assign o_d = 0;
+    assign o_e = 0;
 }
 
 module Module73B {
+    var _d: logic;
+
     inst u0: Module73A::<0>;
     inst u1: Module73A::<1>;
     inst u2: Module73A::<1> (
-        i_a: 0,
-        i_b: 0,
+        i_a: 0 ,
+        i_b: 0 ,
+        o_d: _d,
     );
 }