Miss-formatted SV when omiting port connections

[taichi-ishitani]

Format of generated SV is incorrect when port connections are omitted.

Veryl code

      inst u_bit_field: rggen::rggen_bit_field #(
        WIDTH:          4,
        INITIAL_VALUE:  INITIAL_VALUE,
        SW_WRITE_ONCE:  0,
        TRIGGER:        0
      )(
        i_clk:            i_clk,
        i_rst:            i_rst,
        bit_field_if:     bit_field_sub_if,
        o_write_trigger:  _,
        o_read_trigger:   _,
        o_value:          o_register_0_bit_field_0
      );

Generated SV

            rggen_rggen_bit_field #(
                .WIDTH         (4            ),
                .INITIAL_VALUE (INITIAL_VALUE),
                .SW_WRITE_ONCE (0            ),
                .TRIGGER       (0            )
            ) u_bit_field (
                .i_clk           (i_clk                   ),
                .i_rst_n         (i_rst_n                 ),
                .bit_field_if    (bit_field_sub_if        ),
                .o_write_trigger (                        ),
                .o_read_trigger  (                        ),
                .o_value         (o_register_0_bit_field_0),
                .i_sw_write_enable ('1),
                .i_hw_write_enable ('0),
                .i_hw_write_data   ('0),
                .i_hw_set          ('0),
                .i_hw_clear        ('0),
                .i_value           ('0),
                .i_mask            ('0),
                .
                o_value_unmasked ()

            );