Fix miss fomratted SV

[taichi-ishitani]

Emission of omitted ports is copy of port declarations. Therefore, location info of inst declaration and such port connections are different and this causes such miss emitted SV.
To fix it, location info needs to be adjusted.

fix #1229

[taichi-ishitani]

Expression portions are not aligned because of the same reason but I'm not sure how to adjust it.

veryl/testcases/sv/73_port_default_value.sv

Lines 29 to 49 in 5e607c5

	veryl_testcase___Module73A__0 u0 (
	.i_a (veryl_testcase_Package73::A),
	.i_b (0 ),
	.i_c (0),
	.o_d ( ),
	.o_e ()
	);
	veryl_testcase___Module73A__1 u1 (
	.i_a (veryl_testcase_Package73::A),
	.i_b (1 ),
	.i_c (0),
	.o_d ( ),
	.o_e ()
	);
	veryl_testcase___Module73A__1 u2 (
	.i_a (0 ),
	.i_b (0 ),
	.o_d (_d),
	.i_c (0),
	.o_e ()
	);

[codspeed-hq]

CodSpeed Performance Report

Merging #1237 will not alter performance

_{Comparing taichi-ishitani:fix_miss_formated_sv (a3867d1) with master (6568689)}

Summary

✅ 3 untouched benchmarks

[dalance]

I think that changing aligner structure may be necessary.
Aligner ties the amount of align with the token location, but default port value doesn't have the corresponding token.
I'll consider new aligner architecture.

[dalance]

I'm working on #1245.
In the case of default value only, it was fixed, but combination of explicit and default is not yet.

[dalance]

I'll merge this PR at first, and the remaining issue will be fixed by merging #1245.