NTHU course - Advance SOC

Labs to experiment with Caravel SoC FPGA module design with Verilog & HLS

Student	陳冠晰/Vic Chen
Email	[email protected]

Background Prerequisites

• Vitis HLS
• Xilinx XSIM
• Basic Verilog & HLS coding

Toolchain Prerequisites

• Ubuntu 20.04+
• Xilinx Vitis 2022.1
• GTKWave v3.3.103
• RISC-V GCC Toolchains