CS-21-2021-2022-Proj2

MIPS Single Cycle Processor Extension with SystemVerilog

EDA Playground

All the files uploaded here are also in EDA Playground. You can run the processor there as well.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
README.md		README.md
[Documentation] DeCastro_Hans_201903184_A2.pdf		[Documentation] DeCastro_Hans_201903184_A2.pdf
adder.sv		adder.sv
alu.sv		alu.sv
aludec.sv		aludec.sv
controller.sv		controller.sv
datapath.sv		datapath.sv
design.sv		design.sv
dmem.sv		dmem.sv
flopr.sv		flopr.sv
imem.sv		imem.sv
maindec.sv		maindec.sv
memfile.mem		memfile.mem
mips.sv		mips.sv
mux2.sv		mux2.sv
mux4.sv		mux4.sv
regfile.sv		regfile.sv
shiftleft.sv		shiftleft.sv
signext.sv		signext.sv
sl2.sv		sl2.sv
testbench.sv		testbench.sv
top.sv		top.sv
zeroext.sv		zeroext.sv