Initial commit

.gitignore

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+*.sla
+*.slaspec
+env
+tmp
+*.zip

LICENSE

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+The MIT License (MIT)
+
+Copyright (c) 2020 Ilya Zhuravlev
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

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+# Renesas RL78 processor module for Ghidra
+
+## Installing the module
+
+Download `rl78.zip` from the latest [release](https://github.com/xyzz/ghidra-rl78/releases) and extract it to `Ghidra/Processors`.
+
+## Building from source
+
+Run the following once to set up the build environment:
+
+```
+python3 -mvenv env
+. env/bin/activate
+pip install -r requirements.txt
+```
+
+Ensure Ghidra's `sleigh` utility is in your PATH and then execute:
+
+```
+. env/bin/activate
+./build.sh
+```
+
+The generated `rl78.zip` could then be extracted to `Ghidra/Processors`.

build.sh

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+#!/bin/bash
+set -e
+
+rm -rf tmp
+rm -f rl78.zip
+
+j2 data/languages/rl78.slaspec.in > data/languages/rl78.slaspec
+# Just check it compiles fine
+sleigh -a -u
+
+mkdir -p tmp/rl78/data/languages
+touch tmp/rl78/Module.manifest
+cp data/languages/rl78.{cspec,ldefs,pspec,slaspec} tmp/rl78/data/languages
+cd tmp
+zip -r ../rl78.zip rl78
+cd ..
+ls -la rl78.zip

data/languages/rl78.cspec

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+<?xml version="1.0" encoding="UTF-8"?>
+
+<compiler_spec>
+  <data_organization>  <!-- These tags were generated with gcc 4.2.4 -->
+     <absolute_max_alignment value="0" />
+     <machine_alignment value="2" />
+     <default_alignment value="1" />
+     <default_pointer_alignment value="4" />
+     <pointer_size value="4" />
+     <wchar_size value="4" />
+     <short_size value="2" />
+     <integer_size value="4" />
+     <long_size value="4" />
+     <long_long_size value="8" />
+     <float_size value="4" />
+     <double_size value="8" />
+     <long_double_size value="8" />
+     <size_alignment_map>
+          <entry size="1" alignment="1" />
+          <entry size="2" alignment="2" />
+          <entry size="4" alignment="4" />
+          <entry size="8" alignment="8" />
+     </size_alignment_map>
+  </data_organization>
+  <global>
+    <range space="memory"/>
+  </global>
+  <stackpointer register="SP" space="memory"/>
+  <returnaddress>
+    <varnode space="stack" offset="0" size="3"/>
+  </returnaddress>
+  <default_proto>
+    <prototype name="__stdcall" extrapop="unknown" stackshift="4">
+      <input>
+        <pentry minsize="1" maxsize="2" extension="inttype">
+          <register name="AX"/>
+        </pentry>
+        <pentry minsize="1" maxsize="2" extension="inttype">
+          <register name="BC"/>
+        </pentry>
+        <pentry minsize="1" maxsize="500" align="1">
+          <addr offset="4" space="stack"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="2" extension="inttype">
+          <register name="BC"/>
+        </pentry>
+      </output>
+      <unaffected>
+        <register name="HL"/>
+      </unaffected>
+    </prototype>
+  </default_proto>
+</compiler_spec>

data/languages/rl78.ldefs

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+<?xml version="1.0" encoding="UTF-8"?>
+
+<language_definitions>
+  <language processor="rl78"
+            endian="little"
+            size="16"
+            variant="default"
+            version="1.0"
+            slafile="rl78.sla"
+            processorspec="rl78.pspec"
+            id="RL78:LE:16:default">
+    <description>RL78 processor 16-bit little-endian</description>
+    <compiler name="default" spec="rl78.cspec" id="default"/>
+  </language>
+</language_definitions>

data/languages/rl78.pspec

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+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+  <programcounter register="PC"/>
+  <segmentop space="memory" userop="segment" farpointer="yes">
+    <pcode>
+      <input name="inner" size="2"/>
+      <input name="base" size="2"/>
+      <output name="res" size="4"/>
+      <body><![CDATA[
+        res = (zext(base) << 16) + zext(inner);
+      ]]></body>
+    </pcode>
+  </segmentop>
+</processor_spec>