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[P2] Installation and Data Preloading Issue tancheng#11 - If queue i…
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…s full, will stop receiving new data.
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yuqisun committed Jan 11, 2025
1 parent e6ab286 commit 49b7a97
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Showing 2 changed files with 23 additions and 8 deletions.
2 changes: 1 addition & 1 deletion mem/const/ConstQueueDynamicRTL.py
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ def update_msg():
s.reg_file.waddr[0] @= s.cur
s.reg_file.wdata[0] @= s.recv_const.msg
s.reg_file.wen[0] @= 1
# s.recv_const.rdy @= 0 will stop receive const from inport immediately
# s.recv_const.rdy @= 0 will stop receive const from inport immediately even there's rdy @= 1 in @update
# so will avoid receiving new data when regs full
if s.cur == AddrType(const_mem_size - 1):
s.recv_const.rdy @= 0
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29 changes: 22 additions & 7 deletions mem/const/test/ConstQueueDynamicRTL_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,11 @@
Author : Yuqi Sun
Date : Jan 11, 2025
"""
from ....lib.basic.val_rdy.SinkRTL import SinkRTL
from ..ConstQueueDynamicRTL import ConstQueueDynamicRTL
# from ....lib.basic.en_rdy.test_sinks import TestSinkRTL
# from ....lib.basic.en_rdy.test_srcs import TestSrcRTL
from ....lib.basic.val_rdy.SourceRTL import SourceRTL as ValRdyTestSrcRTL
from ....lib.basic.val_rdy.SourceRTL import SourceRTL
from ....lib.messages import *

#-------------------------------------------------------------------------
Expand All @@ -20,33 +21,47 @@
class TestHarness(Component):

def construct(s, MemUnit, DataType, const_mem_size, src_const):
s.src_const_pkt = ValRdyTestSrcRTL(DataType, src_const)
s.src_const_pkt = SourceRTL(DataType, src_const)
# s.read_data = SinkRTL(DataType, read_data)

s.const_queue = MemUnit(DataType, const_mem_size)
s.src_const_pkt.send //= s.const_queue.recv_const

# s.src_const_pkt.send.rdy //= 0

def line_trace(s):
return s.const_queue.line_trace()


def run_sim(test_harness):
test_harness.elaborate()
test_harness.apply(DefaultPassGroup())
test_harness.sim_reset()

assert 1 < 2

# assert 1 < 2
print(test_harness.line_trace())
# Run simulation
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
test_harness.sim_tick()
print(test_harness.line_trace())

def test_const_queue():
MemUnit = ConstQueueDynamicRTL
DataType = mk_data(16, 1)
DataType = mk_data(4, 1)
const_mem_size = 8
src_const = [DataType(9, 1), DataType(8, 1), DataType(7, 1), DataType(6, 1),
DataType(5, 1), DataType(4, 1), DataType(3, 1), DataType(2, 1),
DataType(1, 1), DataType(-1, 1)]
src_const = [DataType(9, 1), DataType(8, 1), DataType(7, 1)]
# read_data = [DataType(2, 1), DataType(3, 1), DataType(0, 1), DataType(13, 1)]
th = TestHarness(MemUnit, DataType, const_mem_size, src_const)
run_sim(th)

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