Merge pull request tancheng#40 from tancheng/data_mem_xbar

Crossbar based data SRAM

.github/workflows/python-package.yml

@@ -58,14 +58,27 @@ jobs:
       run: |
         mkdir -p build && cd build
         source ${HOME}/venv/bin/activate
+        # Simulation across all tests.
         pytest .. -v --tb=short
-        pytest ../cgra/translate/VectorCGRAKingMeshRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        # Tile translation.
         pytest ../tile/translate/TileRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        # Kingmesh topology CGRA translation.
+        pytest ../cgra/translate/VectorCGRAKingMeshRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        # Separate crossbars CGRA simulation/translation.
+        pytest ../cgra/test/CGRASeparateCrossbarRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
         pytest ../cgra/translate/CGRASeparateCrossbarRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        # 3x2 CGRA performs 2x2 matmul translation.
         pytest ../cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        # 3x3 CGRA performs 2x2 matmul simulation/translation.
         pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short
         pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
+        # Ring network simulation.
         pytest ../noc/PyOCN/pymtl3_net/ringnet/test/RingNetworkRTL_test.py --tb=short -sv
-        pytest --tb=short -sv ../cgra/translate/CGRAWithControllerRTL_test.py --test-verilog --dump-vtb --dump-vcd
+        # CGRA with separate crossbars (for tiles and FUs), crossbar-based data
+        # memory (for multi-bank), and controller.
+        pytest --tb=short -sv ../cgra/translate/CGRAWithCrossbarDataMemRTL_test.py --test-verilog --dump-vtb --dump-vcd
+        # CGRAs are interconnected with ring topology. The CGRA contains
+        # separate crossbars (for tiles and FUs), crossbar-based data memory (for
+        # multi-bank), and controller.
         pytest --tb=short -sv ../scale_out/translate/RingMultiCGRARTL_test.py --test-verilog --dump-vtb --dump-vcd
 

cgra/CGRAWithControllerRTL.py → cgra/CGRAWithCrossbarDataMemRTL.py

@@ -1,10 +1,10 @@
 """
 =========================================================================
-CGRAWithControllerRTL.py
+CGRAWithCrossbarDataMemRTL.py
 =========================================================================
 
 Author : Cheng Tan
-  Date : Dec 4, 2024
+  Date : Dec 13, 2024
 """
 
 from pymtl3 import *
@@ -16,33 +16,38 @@
 from ..lib.basic.val_rdy.ifcs import ValRdySendIfcRTL
 from ..lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL
 from ..lib.opt_type import *
-from ..mem.data.DataMemScalableRTL import DataMemScalableRTL
+from ..mem.data.DataMemWithCrossbarRTL import DataMemWithCrossbarRTL
 from ..noc.ChannelNormalRTL import ChannelNormalRTL
 from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL
 from ..tile.TileSeparateCrossbarRTL import TileSeparateCrossbarRTL
 from ..controller.ControllerRTL import ControllerRTL
 
 
-class CGRAWithControllerRTL(Component):
+class CGRAWithCrossbarDataMemRTL(Component):
 
   def construct(s, DataType, PredicateType, CtrlType, NocPktType,
-                width, height, ctrl_mem_size, data_mem_size, num_ctrl,
-                total_steps, FunctionUnit, FuList, preload_data = None,
-                preload_const = None):
+                CmdType, ControllerIdType, controller_id,
+                width, height, ctrl_mem_size, data_mem_size_global,
+                data_mem_size_per_bank, num_banks_per_cgra, num_ctrl,
+                total_steps, FunctionUnit, FuList, controller2addr_map,
+                preload_data = None, preload_const = None):
 
     s.num_tiles = width * height
     s.num_mesh_ports = 4
-    AddrType = mk_bits(clog2(ctrl_mem_size))
+    CtrlAddrType = mk_bits(clog2(ctrl_mem_size))
+    DataAddrType = mk_bits(clog2(data_mem_size_global))
+    assert(data_mem_size_per_bank * num_banks_per_cgra <= \
+           data_mem_size_global)
 
     # Interfaces
-    s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(s.num_tiles)]
+    s.recv_waddr = [RecvIfcRTL(CtrlAddrType) for _ in range(s.num_tiles)]
     s.recv_wopt = [RecvIfcRTL(CtrlType) for _ in range(s.num_tiles)]
 
     # Explicitly provides the ValRdyRecvIfcRTL in the library, as the
     # translation pass sometimes not able to distinguish the
     # EnRdyRecvIfcRTL from it.
-    s.recv_from_other = ValRdyRecvIfcRTL(NocPktType)
-    s.send_to_other = ValRdySendIfcRTL(NocPktType)
+    s.recv_from_noc = ValRdyRecvIfcRTL(NocPktType)
+    s.send_to_noc = ValRdySendIfcRTL(NocPktType)
 
     # s.recv_towards_controller = RecvIfcRTL(DataType)
     # s.send_from_controller = SendIfcRTL(DataType)
@@ -52,21 +57,38 @@ def construct(s, DataType, PredicateType, CtrlType, NocPktType,
     if preload_const == None:
       preload_const = [[DataType(0, 0)] for _ in range(width*height)]
     s.tile = [TileSeparateCrossbarRTL(DataType, PredicateType, CtrlType,
-                                      ctrl_mem_size, data_mem_size, num_ctrl,
-                                      total_steps, 4, 2, s.num_mesh_ports,
+                                      ctrl_mem_size, data_mem_size_global,
+                                      num_ctrl, total_steps, 4, 2, s.num_mesh_ports,
                                       s.num_mesh_ports, const_list = preload_const[i])
                                       for i in range( s.num_tiles)]
-    s.data_mem = DataMemScalableRTL(DataType, data_mem_size, height, height, preload_data)
-    s.controller = ControllerRTL(NocPktType, DataType, AddrType)
+    s.data_mem = DataMemWithCrossbarRTL(NocPktType, DataType,
+                                        data_mem_size_global,
+                                        data_mem_size_per_bank,
+                                        num_banks_per_cgra, height, height,
+                                        preload_data)
+    s.controller = ControllerRTL(ControllerIdType, CmdType, NocPktType,
+                                 DataType, DataAddrType, controller_id,
+                                 controller2addr_map)
 
     # Connections
 
     # Connects data memory with controller.
-    s.data_mem.recv_from_noc //= s.controller.send_to_master
-    s.data_mem.send_to_noc //= s.controller.recv_from_master
-
-    s.recv_from_other //= s.controller.recv_from_other
-    s.send_to_other //= s.controller.send_to_other
+    # s.data_mem.recv_from_noc //= s.controller.send_to_master
+    # s.data_mem.send_to_noc //= s.controller.recv_from_master
+
+    # The last `recv_raddr` is reserved to connect the controller.
+    s.data_mem.recv_raddr[height] //= s.controller.send_to_master_load_request_addr
+    s.data_mem.recv_waddr[height] //= s.controller.send_to_master_store_request_addr
+    s.data_mem.recv_wdata[height] //= s.controller.send_to_master_store_request_data
+    # Reserved ...
+    s.data_mem.recv_from_noc_rdata //= s.controller.send_to_master_load_response_data
+    # Reserved ...
+    s.data_mem.send_to_noc_load_request_pkt //= s.controller.recv_from_master_load_request_pkt
+    s.data_mem.send_to_noc_load_response_pkt //= s.controller.recv_from_master_load_response_pkt
+    s.data_mem.send_to_noc_store_pkt //= s.controller.recv_from_master_store_request_pkt
+
+    s.recv_from_noc //= s.controller.recv_from_noc
+    s.send_to_noc //= s.controller.send_to_noc
 
     # s.recv_towards_controller //= s.controller.recv_from_master
     # s.send_from_controller //= s.controller.send_to_master