Nxp master trial do not merge #7
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In Meson 0.64, the optimization built-in option now accepts the "plain" value, which will not set any optimization flags. While QEMU does not check the contents of the option and therefore does not suffer any ill effect from the new value, it uses get_option to print the optimization flags in the summary. Clean the code up to remove duplication, and check for -Doptimization=plain at the same time. Reviewed-by: Marc-André Lureau <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
Detect all compilers at the beginning of meson.build, and store the available languages in an array. Reviewed-by: Marc-André Lureau <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
When installing shared libraries, as is the case for libvfio-user.so,
Meson will include relative symbolic links in the output of
"meson introspect --installed":
{
"libvfio-user.so": "/usr/local/lib64/libvfio-user.so",
...
}
In the case of scripts/symlink-install-tree.py, this will
be a symbolic link to a symbolic link but, in any case, there is
no issue in creating it.
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
KVM guest support on 32-bit Arm hosts *has* been removed, so rephrase the sentence describing it. Signed-off-by: Paolo Bonzini <[email protected]>
-machine kernel-irqchip=off is broken for many guest OSes; kernel-irqchip=split is the replacement that works, so remove the deprecated support for the former. Signed-off-by: Paolo Bonzini <[email protected]>
This was deprecated in 6.0 and can now be removed. Signed-off-by: Paolo Bonzini <[email protected]>
These were deprecated in 6.0 and can now be removed. Signed-off-by: Paolo Bonzini <[email protected]>
The new SGX Asynchronous Exit (AEX) notification mechanism (AEX-notify) allows one enclave to receive a notification in the ERESUME after the enclave exit due to an AEX. EDECCSSA is a new SGX user leaf function (ENCLU[EDECCSSA]) to facilitate the AEX notification handling. Whether the hardware supports to create enclave with AEX-notify support is enumerated via CPUID.(EAX=0x12,ECX=0x1):EAX[10]. The new EDECCSSA user leaf function is enumerated via CPUID.(EAX=0x12,ECX=0x0):EAX[11]. Add support to allow to expose the new SGX AEX-notify feature and the new EDECCSSA user leaf function to KVM guest. Link: https://lore.kernel.org/lkml/166760360549.4906.809756297092548496.tip-bot2@tip-bot2/ Link: https://lore.kernel.org/lkml/166760360934.4906.2427175408052308969.tip-bot2@tip-bot2/ Reviewed-by: Yang Zhong <[email protected]> Signed-off-by: Kai Huang <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Only the pmp index that be checked by pmp_hart_has_privs can be used by pmp_get_tlb_size to avoid an error pmp index. Before modification, we may use an error pmp index. For example, we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs. If there is an pmp rule, valid range is [0x4fc, 0x500), then pmp_hart_has_privs will return true; However, this checked pmp index is discarded as pmp_hart_has_privs return bool value. In pmp_is_range_in_tlb, it will traverse all pmp rules. The tlb_sa will be 0x0, and tlb_ea will be 0xfff. If there is a pmp rule [0x10, 0x14), it will be misused as it is legal in pmp_get_tlb_size. As we have already known the correct pmp index, just remove the remove the pmp_is_range_in_tlb and get tlb size directly from pmp_get_tlb_size. Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
We were matching a signed 13-bit range, not a 12-bit range. Expand the commentary within the function and be explicit about all of the ranges. Reported-by: LIU Zhiwei <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
There was a typo using opc_addi instead of opc_add with the two registers. While we're at it, simplify the gating test to al == bl to improve dynamic scheduling even when the output register does not overlap the inputs. Reported-by: LIU Zhiwei <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set base after each step of the address arithmetic instead of before. Return the base register used from tcg_out_tlb_load, so as to keep that register choice localized to that function. Reported-by: LIU Zhiwei <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Bin Meng <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa <[email protected]> Reviewed-by: Bin Meng <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale <[email protected]> Reviewed-by: Weiwei Li <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale <[email protected]> Reviewed-by: Weiwei Li<[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale <[email protected]> Reviewed-by: Weiwei Li <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
When icount is not enabled, there is no API in QEMU that can get the guest instruction number. Translate the guest code in a way that each TB only has one instruction. After executing the instruction, decrease the count by 1 until it reaches 0 where the itrigger fires. Note that only when priviledge matches the itrigger configuration, the count will decrease. Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
The max count in itrigger can be 0x3FFF, which will cause a no trivial translation and execution overload. When icount is enabled, QEMU provides API that can fetch guest instruction number. Thus, we can set an timer for itrigger with the count as deadline. Only when timer expires or priviledge mode changes, do lazy update to count. Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
When QEMU is not in icount mode, execute instruction one by one. The tdata1 can be read directly. When QEMU is in icount mode, use a timer to simulate the itrigger. The tdata1 may be not right because of lazy update of count in tdata1. Thus, We should pack the adjusted count into tdata1 before read it back. Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Avoid calling riscv_itrigger_enabled() when calculate the tbflags. As the itrigger enable status can only be changed when write tdata1, migration load or itrigger fire, update env->itrigger_enabled at these places. Signed-off-by: LIU Zhiwei <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Commit 4024404 changed the way the S irqs are numbered. This breaks when using numa configuration, e.g.: ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \ -m 2G -smp cpus=16 \ -object memory-backend-ram,id=mem0,size=512M \ -object memory-backend-ram,id=mem1,size=512M \ -object memory-backend-ram,id=mem2,size=512M \ -object memory-backend-ram,id=mem3,size=512M \ -numa node,cpus=0-3,memdev=mem0,nodeid=0 \ -numa node,cpus=4-7,memdev=mem1,nodeid=1 \ -numa node,cpus=8-11,memdev=mem2,nodeid=2 \ -numa node,cpus=12-15,memdev=mem3,nodeid=3 leads to: Unexpected error in object_property_find_err() at ../qom/object.c:1304: qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not found This patch makes the nubering of the S irqs identical to what it was before. Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Frédéric Pétrot <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe1 ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
The imsic DT binding[1] has changed and no longer require an ipi-id. The latest IMSIC driver dynamically allocates ipi id if slow-ipi is not defined. Get rid of the unused dt property which may lead to confusion. [1] https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
let tlb_fill() function also increments PMU counter when it is from two-stage translation, so QEMU could also monitor these PMU events when CPU runs in VS/VU mode (like running guest OS). Signed-off-by: Jim Shu <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
…te() sstatus register dump is currently missing in riscv_cpu_dump_state(). As sstatus is a copy of mstatus, which is described in the priv spec, it seems redundant to print the same information twice. Add some comments for this to let people know this is intentional. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by
"Clock Conditioning Circuitry" in the FPGA. The specific clock depends
on the FPGA bitstream & can be locked to one particular {D,P}LL - in the
Icicle Kit Reference Design v2022.09 or later this is/will be the case.
Linux v6.1+ will have a driver for this peripheral and devicetrees that
previously relied on "fixed-frequency" clock nodes have been switched
over to clock-controller nodes. The IOSCB region is represented in QEMU,
but the specific region of it that the CCCs occupy has not so v6.1-rcN
kernels fail to boot in QEMU.
Add the regions as unimplemented so that the status-quo in terms of boot
is maintained.
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map either. FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 are represented in QEMU, leading to load access violations while booting Linux for Icicle if PCIe is enabled as the root port is connected via either FIC 0 or 1. Acked-by: Alistair Francis <[email protected]> Signed-off-by: Conor Dooley <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Following docs/devel/style.rst guidelines, rename stellaris_adc_state -> StellarisADCState. This also remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
The typedef and definitions are generated by the OBJECT_DECLARE_TYPE macro in "hw/arm/bcm2836.h": 20 #define TYPE_BCM283X "bcm283x" 21 OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X) The script ran in commit a489d19 ("Use OBJECT_DECLARE_TYPE when possible") missed them because they are declared in a different file unit. Remove them. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
NPCM7XX models have been commited after the conversion from commit 8063396 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Manually convert them. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
The structure is named SECUREECState. Rename the type accordingly. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
This model was merged few days before the QOM cleanup from commit 8063396 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible") was pulled and merged. Manually adapt. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
macro call, to avoid after a QOM refactor:
hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a definition
DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
^
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Edgar E. Iglesias <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
macro call, to avoid after a QOM refactor:
hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be a definition
DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
^
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Edgar E. Iglesias <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3 write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is enabled and exposed to the guest. As a result EL3 writes of that bit are ignored. Cc: [email protected] Signed-off-by: Evgeny Iakovlev <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Peter Maydell <[email protected]>
…/pmaydell/qemu-arm into staging target-arm queue: hw/arm/stm32f405: correctly describe the memory layout hw/arm: Add Olimex H405 board cubieboard: Support booting from an SD card image with u-boot on it target/arm: Fix sve_probe_page target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled various code cleanups # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmPBZmYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3rDdD/9GlrH14yP/2WQZJVJxzXkf # ltO1pvX/AfeNPGy3F8T+kncKspIUeJ8BQNrZKYPWkH1WgAAT3lVH/cUbAlr8UD6W # p2t64ZdQAURuEw3kqtyUVOUeIxzg29cEQyW/9uchA3QPb9xDtiq6KLpAzifDzo6o # 2JE4/NytUJSKxFr5hnyxRTtOYPEMLShBSPvPzU0/BPq7VPyPhT4rqojhpx9uZpVc # h4mfVm9cpF0y3ThBR37M0nhEGJywB/6zOsZ49bm06MFFTwasZ4P0w0fcKhbvrFvX # PHVlNOvyT1oxch5ErN+KULZLByiWy0/Nw85V8P9R+1hU6nncQPM5paB6Y5HUCTKv # wa9gp38V8323fsHg2EEV/PYRdcmRWSBHOq9HPDjIIJlG9nvfXn9O69kDlhnst44b # Fz27XiGJOKY+f20l0J0KzaOnnjw54aeo5tc5WUDbBiZ/btsAHBGQAg7JghmoLkhb # rlvJFgGdG99IuBqJH69dJQ8n/R9bGDRu6X0i1ir3d3C2nY9HYaWUZMyyxOw9dV43 # igQHupOzyYbSyy9+40xz611P0h2k2d90P61Vi41D9ig4Du+I4Vftjqj9mi/Z829k # W1JE5wpKWcDeIXFYLWCZuiOyTCCFBWiWgDJz/zQf7AYma0AWA9gpKrTh2+3EFfqy # VsvMR2T6kmS3FId50bW5OQ== # =D+ib # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 14:10:46 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "[email protected]" # gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm: (38 commits) target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock' hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic' hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE() hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name hw/arm/stellaris: Drop useless casts from void * to pointer hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name hw/arm/omap: Drop useless casts from void * to pointer hw/gpio/omap_gpio: Add local variable to avoid embedded cast hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState hw/arm: Remove unreachable code calling pflash_cfi01_register() hw/arm/vexpress: Remove dead code in vexpress_common_init() hw/arm/z2: Use the IEC binary prefix definitions hw/arm/omap_sx1: Use the IEC binary prefix definitions hw/arm/omap_sx1: Remove unused 'total_ram' definitions ... Signed-off-by: Peter Maydell <[email protected]>
uart use charbackend ./build/qemu-system-arm -nographic -machine rt595-m33,boot-base-addr=0x280000 \ -kernel /home/shared/temp/hello_world.out \ -serial chardev:char2 -chardev pipe,id=char2,path=/tmp/pipe or simplely ./build/qemu-system-arm -nographic -machine rt595-m33,boot-base-addr=0x280000 \ -kernel /home/shared/temp/hello_world.out Signed-off-by: Hake Huang <[email protected]>
add sd support add hsgpio and sec_hsgpio support ./build/qemu-system-arm -nographic -machine rt595-m33,boot-base-addr=0x280000 \ -kernel /home/shared/temp/sdcard_polling.out \ -drive file=/home/shared/temp/sd1.img,if=sd,index=0,format=raw or simplely ./build/qemu-system-arm -nographic -machine rt595-m33,boot-base-addr=0x280000 \ -kernel /home/shared/temp/sdcard_polling.out -sd /home/shared/temp/sd1.img Signed-off-by: Hake Huang <[email protected]>
enable pmc wakeup feature Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
./configure --target-list=xtensa-softmmu Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Hake Huang <[email protected]>
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try to start a customer qemu demo mode for zephyr project