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loongarch: add memory fence & support tmp register for atomic #263

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zherczeg merged 1 commit into zherczeg:master from lrzlin:loong-update

Aug 12, 2024

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lrzlin commented Aug 12, 2024

Implement LoongArch dbar 0 memory fence, which is a full memory barrier just like fence iorw, iorw on RISC-V.

Also support tmp register for atomic, it worth noticing that TMP_REG2 seems to have collision issues, so I use TMP_REG3 instead.

Done: #262


          loongarch: add memory fence & support tmp register for atomic

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zherczeg left a comment

LGTM

zherczeg merged commit 4dd388a into zherczeg:master

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