refactor: replace cloneType with chiselTypeOf

zhutmost · Aug 4, 2024 · 663d620 · 663d620
1 parent 14b050c
commit 663d620
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Showing 4 changed files with 9 additions and 9 deletions.
diff --git a/chipmunk/src/stream/StreamArbiter.scala b/chipmunk/src/stream/StreamArbiter.scala
@@ -6,7 +6,7 @@ import chisel3.util._
 
 object StreamArbiter {
   def roundRobin[T <: Data](ins: Seq[StreamIO[T]]): StreamIO[T] = {
-    val uArb = Module(new RRArbiter(ins.head.bits.cloneType, ins.length))
+    val uArb = Module(new RRArbiter(chiselTypeOf(ins.head.bits), ins.length))
     (uArb.io.in zip ins).foreach { x =>
       x._1.valid := x._2.valid
       x._1.bits  := x._2.bits
@@ -16,7 +16,7 @@ object StreamArbiter {
   }
 
   def lowerFirst[T <: Data](ins: Seq[StreamIO[T]]): StreamIO[T] = {
-    val uArb = Module(new Arbiter(ins.head.bits.cloneType, ins.length))
+    val uArb = Module(new Arbiter(chiselTypeOf(ins.head.bits), ins.length))
     (uArb.io.in zip ins).foreach { x =>
       x._1.valid := x._2.valid
       x._1.bits  := x._2.bits

diff --git a/chipmunk/src/stream/StreamDelay.scala b/chipmunk/src/stream/StreamDelay.scala
@@ -10,7 +10,7 @@ object StreamDelay {
     if (cycles == 0) {
       in
     } else {
-      val uStreamDelay = Module(new StreamDelay(in.bits.cloneType, delayWidth = log2Ceil(cycles + 1)))
+      val uStreamDelay = Module(new StreamDelay(chiselTypeOf(in.bits), delayWidth = log2Ceil(cycles + 1)))
       uStreamDelay.io.in << in
       uStreamDelay.io.targetDelay := cycles.U
       uStreamDelay.io.out
@@ -23,7 +23,7 @@ object StreamDelay {
     if (maxCycles == minCycles) {
       fixed(in, maxCycles)
     } else {
-      val uStreamDelay = Module(new StreamDelay(in.bits.cloneType, log2Ceil(maxCycles + 1)))
+      val uStreamDelay = Module(new StreamDelay(chiselTypeOf(in.bits), log2Ceil(maxCycles + 1)))
 
       val randomDelayRange: Int = maxCycles - minCycles - 1
       val randomDelayWidth: Int = log2Ceil(randomDelayRange)
@@ -88,7 +88,7 @@ class StreamDelay[T <: Data](gen: T, delayWidth: Int) extends Module {
       }
     }
   }
-  import fsm.{sIdle, sCount, sPend}
+  import fsm.{sCount, sIdle, sPend}
 
   val counterInc: Bool      = fsm.isActive(sCount)
   val counterReset: Bool    = fsm.isActive(sIdle) || fsm.isEntering(sPend)

diff --git a/chipmunk/src/stream/StreamDemux.scala b/chipmunk/src/stream/StreamDemux.scala
@@ -7,14 +7,14 @@ import chisel3.util._
 /** Demultiplex one stream into multiple output streams, always selecting only one at a time. */
 object StreamDemux {
   def apply[T <: Data](in: StreamIO[T], select: UInt, num: Int): Vec[StreamIO[T]] = {
-    val c = Module(new StreamDemux(in.bits.cloneType, num))
+    val c = Module(new StreamDemux(chiselTypeOf(in.bits), num))
     c.io.in << in
     c.io.select := select
     c.io.outs
   }
 
   def apply[T <: Data](in: StreamIO[T], select: StreamIO[UInt], num: Int): Vec[StreamIO[T]] = {
-    val c = Module(new StreamDemux(in.bits.cloneType, num))
+    val c = Module(new StreamDemux(chiselTypeOf(in.bits), num))
     c.io.in << in
     select >> c.io.createSelectStream()
     c.io.outs

diff --git a/chipmunk/src/stream/StreamMux.scala b/chipmunk/src/stream/StreamMux.scala
@@ -7,14 +7,14 @@ import chisel3.util._
 /** Multiplex multiple streams into a single one, always only processing one at a time. */
 object StreamMux {
   def apply[T <: Data](select: UInt, ins: Vec[StreamIO[T]]): StreamIO[T] = {
-    val uMux = Module(new StreamMux(ins(0).bits.cloneType, ins.length))
+    val uMux = Module(new StreamMux(chiselTypeOf(ins(0).bits), ins.length))
     (uMux.io.ins zip ins).foreach(x => x._1 << x._2)
     uMux.io.select := select
     uMux.io.out
   }
 
   def apply[T <: Data](select: StreamIO[UInt], ins: Vec[StreamIO[T]]): StreamIO[T] = {
-    val uMux = Module(new StreamMux(ins(0).bits.cloneType, ins.length))
+    val uMux = Module(new StreamMux(chiselTypeOf(ins(0).bits), ins.length))
     (uMux.io.ins zip ins).foreach(x => x._1 << x._2)
     select >> uMux.io.createSelectStream()
     uMux.io.out