fix flush in ID, address mismatch

lake/spec/address_generator.py

@@ -14,6 +14,10 @@ def __init__(self, dimensionality=6, recurrence=True):
         self.total_num_addrs = None
         self.addr_width = None
         self.exploit_recurrence = recurrence
+        self.width_mult = 1
+
+    def set_width_mult(self, width_mult):
+        self.width_mult = width_mult
 
     def gen_hardware(self, memports=None, id: IterationDomain = None, pos_reset=False):
         assert memports is not None
@@ -26,7 +30,7 @@ def gen_hardware(self, memports=None, id: IterationDomain = None, pos_reset=Fals
             memport: MemoryPort
             self.total_num_addrs += memport.get_num_addrs()
 
-        self.addr_width = kts.clog2(self.total_num_addrs)
+        self.addr_width = kts.clog2(self.total_num_addrs) + kts.clog2(self.width_mult)
         module_name = f"addr_gen_{self.dimensionality_support}_{self.addr_width}"
         super().__init__(name=module_name)
         ##########
@@ -42,8 +46,8 @@ def gen_hardware(self, memports=None, id: IterationDomain = None, pos_reset=Fals
         ### Inputs
         # self._clk = self.clock("clk")
         # self._rst_n = self.reset("rst_n")
-        self._flush = self.input("flush", 1)
-        self.add_attribute("sync-reset=flush")
+        # self._flush = self.input("flush", 1)
+        # self.add_attribute("sync-reset=flush")
         self._step = self.input("step", 1)
         self._mux_sel = self.input("mux_sel", max(kts.clog2(self.dimensionality_support), 1))
         self._restart = self.input("restart", 1)

lake/spec/component.py

@@ -40,6 +40,8 @@ def __init__(self, name=None):
         self._name_to_var_cfg = {}
         self._clk = self.clock('clk')
         self._rst_n = self.clock('rst_n')
+        self._flush = self.input("flush", 1)
+        self.add_attribute("sync-reset=flush")
 
     def get_clock(self):
         return self._clk

lake/spec/iteration_domain.py

@@ -132,14 +132,6 @@ def gen_hardware(self, pos_reset=False):
         self.config_space_fixed = True
         self._assemble_cfg_memory_input()
 
-        # if self.add_flush:
-        if True:
-            self.add_attribute("sync-reset=flush")
-            kts.passes.auto_insert_sync_reset(self.internal_generator)
-            # flush_port = self.internal_generator.get_port("flush")
-            # flush_port.add_attribute(ControlSignalAttr(True))
-
-
     @always_comb
     # Find lowest ready
     def set_mux_sel(self):
@@ -171,6 +163,8 @@ def set_inc(self, idx):
     def dim_counter_update(self, idx):
         if ~self._rst_n:
             self._dim_counter[idx] = 0
+        elif self._flush:
+            self._dim_counter[idx] = 0
         else:
             if self._clear[idx]:
                 self._dim_counter[idx] = 0
@@ -181,6 +175,8 @@ def dim_counter_update(self, idx):
     def max_value_update(self, idx):
         if ~self._rst_n:
             self._max_value[idx] = 0
+        elif self._flush:
+            self._max_value[idx] = 0
         else:
             if self._clear[idx]:
                 self._max_value[idx] = 0

lake/spec/port.py

@@ -164,7 +164,8 @@ def gen_hardware(self, pos_reset=False, dimensionality=None, external_id=None):
                     # self.wire(self._data_out_lcl, ub_interface['data'])
 
                     self._full_addr_in = self.input("addr_in", width=self.port_ag_width)
-                    self._addr_out = self.output("addr_out", width=self.port_ag_width)
+                    # self._addr_out = self.output("addr_out", width=self.port_ag_width)
+                    self._addr_out = self.output("addr_out", width=(self.port_ag_width - kts.clog2(self.get_fw())))
                     self._sg_step_in = self.input("sg_step_in", width=1)
                     # This will be used to send out to the AG/ID, etc.
                     # This is also telling us if we are making a memory read this cycle
@@ -310,8 +311,9 @@ def addresses_to_write_ff():
                     # Address out is whichever address is being pointed to by the linear read address
                     # self.wire(self._addr_out, kts.concat(self._full_addr_in[self._full_addr_in.width - 1, self._full_addr_in.width - sub_addr_bits],
                     #  self._full_addr_in[self._full_addr_in.width - 1, self._full_addr_in.width - sram_addr_bits]))
-                    self.wire(self._addr_out, kts.concat(self._last_write_addr[self._full_addr_in.width - 1, self._full_addr_in.width - sub_addr_bits],
-                                                         addresses_to_write[self._linear_wcb_read]))
+                    # self.wire(self._addr_out, kts.concat(self._last_write_addr[self._full_addr_in.width - 1, self._full_addr_in.width - sub_addr_bits],
+                    #                                      addresses_to_write[self._linear_wcb_read]))
+                    self.wire(self._addr_out, addresses_to_write[self._linear_wcb_read])
 
                     # write_memory_out is just the mp_interface's ready and the sticky bit
                     self.wire(self._write_memory_out_lcl, self._mp_intf['ready'] & self._write_can_commit_sticky[self._linear_wcb_read])
@@ -626,7 +628,7 @@ def new_address_comb():
                     # Will need the address and enable/step from the external AG/SG/ID
                     assert self.port_ag_width is not None
                     self._full_addr_in = self.input("addr_in", width=self.port_ag_width)
-                    self._addr_out = self.output("addr_out", width=self.port_ag_width)
+                    self._addr_out = self.output("addr_out", width=(self.port_ag_width - kts.clog2(self.get_fw())))
                     self._sg_step_in = self.input("sg_step_in", width=1)
                     self._grant = self.input("grant", width=1)
                     # This will be used to send out to the AG/ID, etc.

lake/spec/schedule_generator.py

@@ -46,8 +46,8 @@ def gen_hardware(self, id: IterationDomain = None, num_comparisons: int = 1, pos
         # self._clk = self.clock("clk")
         # self._rst_n = self.reset("rst_n")
 
-        self._flush = self.input("flush", 1)
-        self.add_attribute("sync-reset=flush")
+        # self._flush = self.input("flush", 1)
+        # self.add_attribute("sync-reset=flush")
         self._clk_ctr = add_counter(self, "clk_ctr", bitwidth=self.total_cycle_width, increment=kts.const(1, 1),
                                     clear=self._flush)
         self._mux_sel = self.input("mux_sel", max(kts.clog2(self.dimensionality_support), 1))
@@ -182,10 +182,6 @@ def gen_hardware(self, id: IterationDomain = None, num_comparisons: int = 1, pos
         ##########
         ### Config Regs
         ### Inputs
-        # self._clk = self.clock("clk")
-        # self._rst_n = self.reset("rst_n")
-        self._flush = self.input("flush", 1)
-        self.add_attribute("sync-reset=flush")
 
         # Still accept the iterators/mux_sel
         self._mux_sel = self.input("mux_sel", max(kts.clog2(self.dimensionality_support), 1))

lake/spec/spec.py

@@ -330,6 +330,13 @@ def generate_hardware(self) -> None:
             # Port needs to know about the dimensionality in case of a vectorized port to
             # build the proper hardware within the port
             port_id.gen_hardware()
+
+            # If we are using the optimized implementation, it is crucial
+            # make the address generator wider than the main memory (use word-level addressing)
+            if self.opt_rv:
+                width_mult = port.get_fw()
+                port_ag.set_width_mult(width_mult)
+
             port_ag.gen_hardware(memports_, port_id)
             port.set_port_ag_width(port_ag.get_address_width())