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Spider: ethernet: fix ethernet issues and extend port usage #155

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merged 4 commits into from
Nov 24, 2023
Merged

Spider: ethernet: fix ethernet issues and extend port usage #155

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23bb99f
spider: build: remove pedantic flag
valeriosetti Nov 14, 2023
c45d215
spider: ethernet: fix for using ports TSN1 and TSN2
valeriosetti Nov 14, 2023
14085bf
spider: core: add L1 cache clearing function
valeriosetti Nov 22, 2023
d2ec66c
spider: ethernet: clear L1 cache before reading RX descriptors
valeriosetti Nov 22, 2023
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1 change: 0 additions & 1 deletion goil/templates/config/cortex-a-r/armv8/spider/buildOptions.oil
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Expand Up @@ -9,7 +9,6 @@ CPU buildOptions {
*/
// COMMONFLAGS = "-g"; // Produce debugging information
COMMONFLAGS = "-Wall"; // All warnings on
COMMONFLAGS = "-pedantic";
COMMONFLAGS = "-Wformat";
COMMONFLAGS = "-std=c99";
COMMONFLAGS = "-mcpu=cortex-r52"; // Compile for arm r52
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1 change: 1 addition & 0 deletions goil/templates/config/cortex-a-r/armv8/spider/config.oil
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Expand Up @@ -56,6 +56,7 @@ CPU spider {
CFILE = "tpl_stubs.c";
CFILE = "tpl_irq.c";
CFILE = "tpl_vector_table_ns.s";
CFILE = "spider_utils.c";
};

LIBRARY serial {
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48 changes: 31 additions & 17 deletions libraries/drivers/ethernet/renesas/eth_serdes.c
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Expand Up @@ -86,7 +86,7 @@ static int eth_serdes_wait_reset(void)
{
int ch, ret;

for (ch = 0; ch < ETH_SERDES_CH_NUM; ch++) {
for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0180U);
ret = eth_serdes_wait_for_update(ch, 0x026C, BIT(0), BIT(0), ETH_TIMEOUT_COUNT);
if (ret != 0) {
Expand All @@ -105,8 +105,10 @@ static int eth_serdes_initialize_SRAM(void)
return ret;
}

ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0180);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x026C, 0x3);
for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0180);
ETH_SERDES_REG_WRITE(ch, 0x026C, 0x3);
}

for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0300U);
Expand All @@ -121,22 +123,27 @@ static int eth_serdes_initialize_SRAM(void)

static void eth_serdes_set_SGMII_common_settings(void)
{
int ch;
/* Steps S.4.1 to S.4.5 */
ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0180);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x0244, 0x97);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01D0, 0x60);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01D8, 0x2200);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01D4, 0x0);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x01E0, 0x3D);
for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0180);
ETH_SERDES_REG_WRITE(ch, 0x0244, 0x97);
ETH_SERDES_REG_WRITE(ch, 0x01D0, 0x60);
ETH_SERDES_REG_WRITE(ch, 0x01D8, 0x2200);
ETH_SERDES_REG_WRITE(ch, 0x01D4, 0x0);
ETH_SERDES_REG_WRITE(ch, 0x01E0, 0x3D);
}
}

static int eth_serdes_PHY_soft_reset(void)
{
int ret;
int ch, ret;

/* Step:5 */
ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0380);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x0000, 0x8000);
for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0380);
ETH_SERDES_REG_WRITE(ch, 0x0000, 0x8000);
}

/* Step:6 */
ret = eth_serdes_wait_reset();
Expand All @@ -145,14 +152,21 @@ static int eth_serdes_PHY_soft_reset(void)
}

/* Step:7 */
ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0180U);
ETH_SERDES_REG_WRITE(ETH_SERDES_XPCS_CH0, 0x026CU, 0x00000003UL);
for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0180U);
ETH_SERDES_REG_WRITE(ch, 0x026CU, 0x00000003UL);
}

/* Step:8 */
ETH_SERDES_SEL_BANK(ETH_SERDES_XPCS_CH0, 0x0380U);
ret = eth_serdes_wait_for_update(ETH_SERDES_XPCS_CH0, 0x0000U, BIT(15), 0UL, ETH_TIMEOUT_COUNT);
for (ch = ETH_SERDES_XPCS_CH0; ch < ETH_SERDES_CH_NUM; ch++) {
ETH_SERDES_SEL_BANK(ch, 0x0380U);
ret = eth_serdes_wait_for_update(ch, 0x0000U, BIT(15), 0UL, ETH_TIMEOUT_COUNT);
if (ret != 0) {
return ret;
}
}

return ret;
return 0;
}

static int eth_serdes_channel_SGMII_common_configuration(uint32 ch)
Expand Down
20 changes: 11 additions & 9 deletions libraries/drivers/ethernet/renesas/rswitch.c
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Expand Up @@ -3,6 +3,7 @@
#include "rswitch.h"
#include "rswitch_regs.h"
#include "err_codes.h"
#include "spider_utils.h"
#include <string.h>

#define PORT_TSNA_N 3
Expand Down Expand Up @@ -778,31 +779,31 @@ static int rswitch_phy_init(struct rswitch_etha *etha)
int ret;

/* Reset */
CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0xC04A, &reg_data));
CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0xC04A, &reg_data));
reg_data |= BIT(15);
CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0xC04A, &reg_data));
CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0xC04A, &reg_data)); /* MCAL does it twice... */
CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0xC04A, &reg_data));
CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0xC04A, &reg_data)); /* MCAL does it twice... */

/* Check mode */
CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0xC04A, &reg_data));
CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0xC04A, &reg_data));
if ((reg_data & 0x7) != 0x4 ) { /* 4 stands for SGMII */
reg_data &= ~0x7;
reg_data |= BIT(15) | 0x4;
CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0xC04A, &reg_data));
CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0xC04A, &reg_data));

/* Run SERDES Init */
CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0x800F, &reg_data));
CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0x800F, &reg_data));
reg_data |= BIT(15) | BIT(13);
CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0x800F, &reg_data));
CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0x800F, &reg_data));

reg_data = 0x0U;
do {
CHECK_RET(rswitch_mii_read(etha, 1, etha->port_num + 1, 0x800F, &reg_data));
CHECK_RET(rswitch_mii_read(etha, etha->port_num + 1, 1, 0x800F, &reg_data));
} while (reg_data & BIT(15));

/* Auto SERDES Init Disable */
reg_data &= ~BIT(13);
CHECK_RET(rswitch_mii_write(etha, 1, etha->port_num + 1, 0x800F, &reg_data));
CHECK_RET(rswitch_mii_write(etha, etha->port_num + 1, 1, 0x800F, &reg_data));
}

return 0;
Expand Down Expand Up @@ -929,6 +930,7 @@ TASK(gwca1_rx_tx_task) {
if (chain->irq_triggered != 0) {
/* Go through the descriptors chain to parse received data */
while (1) {
invalidate_data_cache_by_address(rx_ring, sizeof(rx_ring));
ts_desc = &(chain->ts_ring[chain->next_index]);
/* Stop once we get to a descriptor that was not modified */
if (ts_desc->die_dt == (DT_FEMPTY | DIE)) {
Expand Down
22 changes: 22 additions & 0 deletions machines/cortex-a-r/armv8/spider/spider_utils.c
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@@ -0,0 +1,22 @@
#include "emblib.h"

#define DCACHE_LINE_SIZE 64

void invalidate_data_cache_by_address(volatile void *addr, sint32 dsize)
{
if ( dsize > 0 ) {
sint32 op_size = dsize + (((uint32)addr) & (DCACHE_LINE_SIZE - 1U));
uint32 op_addr = (uint32)addr;

__asm__ volatile ("dsb");

do {
cp15_write32(0, 7, 6, 1, op_addr);
op_addr += DCACHE_LINE_SIZE;
op_size -= DCACHE_LINE_SIZE;
} while ( op_size > 0 );

__asm__ volatile ("dsb");
__asm__ volatile ("isb");
}
}
3 changes: 3 additions & 0 deletions machines/cortex-a-r/armv8/spider/spider_utils.h
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@@ -0,0 +1,3 @@


void invalidate_data_cache_by_address(volatile void *addr, sint32 dsize);