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Ability to import specific module from Verilog/model from BLIF without making its io the block's IO #398
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…t making its io the block's IO
Codecov Report
@@ Coverage Diff @@
## development #398 +/- ##
===============================================
- Coverage 90.71% 90.62% -0.10%
===============================================
Files 24 24
Lines 5988 6013 +25
===============================================
+ Hits 5432 5449 +17
- Misses 556 564 +8
Continue to review full report at Codecov.
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Improve rom verilog output
Improve Verilog output when a memory doesn't have any writes
…t making its io the block's IO
…o submodule-import
Don't generate nands on BLIF import
…t making its io the block's IO
…o submodule-import
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This will import the Verilog module without making its i/o wires the block's i/o wires. Instead, it returns an object whose attributes are input/output wires, accessible via the name of the wires defined on the Verilog module.
Given this Verilog file
You can import it like so
foo.x
andfoo.y
areWireVector
s, notInput
, and they are named with internal names so the module can be imported multiple times without clashes. Similarly,foo.z
isWireVector
, notOutput
. All these wires can be connected to others like normal:The key is the
**as_block**
parameter you pass toinput_from_verilog
, which will determine if block-level I/O is created, or instead a "submodule".This PR also adds support for importing particular models from a BLIF file (since the
input_from_verilog()
function basically wraps the call toinput_from_blif()
).