Ability to import specific module from Verilog/model from BLIF without making its io the block's IO#398

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mdko wants to merge 11 commits intoUCSBarchlab:developmentfrom pllab:submodule-import

+322-34

Commits on Jul 9, 2021

Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
mdko
committed

Commits on Jul 23, 2021

improve rom verilog output
vegaluisjose
committed

Commits on Aug 4, 2021

Merge pull request UCSBarchlab#399 from vegaluisjose/improve_rom
mdko
authored
Improve Verilog output when a memory doesn't have any writes
mdko
committed
Merge pull request UCSBarchlab#400 from pllab/verilog-output-update
mdko
authored
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
mdko
committed
Merge branch 'submodule-import' of https://github.com/pllab/PyRTL into submodule-import
mdko
committed
Don't generate nands on BLIF import
mdko
committed
Merge pull request UCSBarchlab#401 from pllab/blif-import-update
mdko
authored
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
mdko
committed
Merge branch 'submodule-import' of https://github.com/pllab/PyRTL into submodule-import
mdko
committed