Fix various inaccuracies in the RISC-V lifter #64
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The shift value must be treated as an unsigned integer otherwise a shift value such as '0b11111' would be interpreted as -1 instead of 31.
For arithmetic shift instructions, use the .sra() method provided by VexValue. For R-type shift instructions, extract the shift amount by reading the lower 5 bits of the register (previously the shift amount was incorrectly extracted from the register index, not the register value).
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This patchset fixes several issues where the provided lifter for the RISC-V 32-bit base instruction set would not correctly capture the semantics of RISC-V instruction as mandated by the RISC-V specification. As illustrated in #62, this causes angr to miss execution paths during symbolic execution, when used with this lifter. With this patchset applied, angr finds all 625 paths in the example binary provided in #62.
Specifically, this patchset fixes the following issues:
With these patches applied, angr passes the riscv-tests for the 32-bit base instruction set (rv32i). I did not test the lifter for additional instruction set extensions (e.g. the M- or C-extension).
Fixes #62
CC: @twizmwazin