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Build(deps): Bump third_party/surelog from `5120036` to `298a9cd` #6090

Job	Run time
Emit Workflow Info	0s
Build Synlig Release	21m 25s
Build tools	10m 22s
Build Plugin	21m 4s
Style check	1m 38s
Build Synlig (ASAN)	10m 0s
Build Package	17m 21s
Verify README Correctness (Installation From Sources)	43m 25s
Build PySynlig	20m 36s
Large Designs Tests / Ibex (Vivado synthesis)	6m 27s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	30m 15s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 11s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 5s
Large Designs Tests / Opentitan parsing (quick)	5m 28s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 31s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	14m 6s
Large Designs Tests / Opentitan (synthesis)	52m 27s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 33s
Formal Verification Tests / simple	17m 24s
Large Designs Tests / Black Parrot (ASIC synthesis)	39m 31s
Formal Verification Tests / sv2v	16m 43s
Formal Verification Tests / yosys	14m 14s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	40m 43s
Parsing Tests / Test read_systemverilog release	4m 25s
Parsing Tests / Test read_uhdm release	4m 7s
Parsing Tests / Test read_systemverilog plugin	4m 27s
Parsing Tests / Test read_uhdm plugin	4m 15s
Parsing Tests / Test read_systemverilog asan	36m 6s
Parsing Tests / Test read_uhdm asan	25m 16s
Parsing Tests / Summary Generation	1m 31s
Parsing Tests / Generate AST diff	1m 35s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	8h 20m 11s

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