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Build(deps): Bump third_party/sv2v from `e9c01d2` to `12618d5` #6100

Job	Run time
Style check	1m 31s
Build Synlig Release	4m 14s
Build Plugin	3m 46s
Build tools	10m 38s
Build Synlig (ASAN)	6m 57s
Verify README Correctness (Installation From Sources)	41m 1s
Emit Workflow Info	0s
Build Package	4m 19s
Build PySynlig	8m 47s
Parsing Tests / Test read_systemverilog release	4m 35s
Parsing Tests / Test read_uhdm release	4m 8s
Large Designs Tests / Ibex (Vivado synthesis)	6m 22s
Parsing Tests / Test read_systemverilog plugin	4m 39s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 19s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	32m 24s
Parsing Tests / Test read_uhdm plugin	4m 12s
Parsing Tests / Test read_systemverilog asan	35m 27s
Parsing Tests / Test read_uhdm asan	25m 29s
Large Designs Tests / Black Parrot (ASIC synthesis)	38m 15s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 38s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 14s
Large Designs Tests / Opentitan parsing (quick)	5m 18s
Large Designs Tests / Opentitan (synthesis)	55m 12s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 9s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 24s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	40m 23s
Formal Verification Tests / simple	17m 21s
Formal Verification Tests / sv2v	17m 16s
Formal Verification Tests / yosys	14m 25s
Parsing Tests / Summary Generation	1m 32s
Parsing Tests / Generate AST diff	1m 53s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 21m 48s

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