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Build(deps): Bump third_party/sv2v from e9c01d2 to aa0a885 #6101

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Build(deps): Bump third_party/sv2v from e9c01d2 to aa0a885

Build(deps): Bump third_party/sv2v from e9c01d2 to aa0a885 #6101

Triggered via pull request December 16, 2024 07:17
@dependabotdependabot[bot]
opened #2708
dependabot/submodules/third_party/sv2v-aa0a885
Status Failure
Total duration 1h 5m 59s
Artifacts 49

main.yml

on: pull_request
Matrix: build-binaries
Build tools
11m 28s
Build tools
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 38s
Style check
Verify README Correctness (Installation From Sources)
41m 34s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 43s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
12m 0s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
31m 50s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
57m 3s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 32s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 51s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
40m 40s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
39m 25s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 20s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 52s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 30s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

1 error and 4 warnings
Formal Verification Tests / sv2v
Process completed with exit code 1.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
42 MB
bp_e_bp_unicore_cfg.edif
3.92 MB
bsg-logs
5.57 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.9 MB
formal-verification-logs-sv2v
65.8 MB
formal-verification-logs-yosys
50.1 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
4.57 MB
opentitan-logs-quick
827 KB
plots_binaries-asan
47.7 KB
plots_binaries-package
27.7 KB
plots_binaries-plugin
27 KB
plots_binaries-pysynlig
57.1 KB
plots_binaries-release
29.1 KB
plots_blackparrot_synth_asic
241 KB
plots_blackparrot_synth_xilinx
111 KB
plots_blackparrot_synth_xilinx_python
228 KB
plots_build_tools
82.3 KB
plots_formal_verification_simple
112 KB
plots_formal_verification_sv2v
119 KB
plots_formal_verification_yosys
95.8 KB
plots_ibex_synth
47.3 KB
plots_ibex_synth_f4pga
85.1 KB
plots_opentitan_9d82960888_synth
176 KB
plots_opentitan_parse_report_full
87.3 KB
plots_opentitan_parse_report_quick
40 KB
plots_opentitan_synth
306 KB
plots_tests_asan_read_systemverilog
221 KB
plots_tests_asan_read_uhdm
170 KB
plots_tests_plugin_read_systemverilog
37.4 KB
plots_tests_plugin_read_uhdm
34.7 KB
plots_tests_release_read_systemverilog
36.4 KB
plots_tests_release_read_uhdm
32.4 KB
plots_veer_synth
38.9 KB
python_bp_e_bp_unicore_cfg.edif
3.92 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.48 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.4 MB
top_artya7.bit
119 KB