Parameter typespec issue #5265

Job	Run time
Build sv2v	1m 25s
Build Binaries	4m 31s
Emit Workflow Info	0s
Build Binaries (for Debian)	7m 27s
Style check	1m 21s
Build Binaries (ASAN)	8m 34s
Test "Installation from source" from README	52m 37s
Upload GHA event file	3s
Test With Packaged Yosys	2m 3s
Large Designs Tests / Ibex (Vivado synthesis)	5m 54s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 22s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	28m 41s
Large Designs Tests / Black Parrot (ASIC synthesis)	1h 8m 45s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	19m 40s
Large Designs Tests / Opentitan parsing (full/top-down)	16m 45s
Large Designs Tests / Opentitan (synthesis)	1h 36m 29s
Large Designs Tests / VeeR-EH1 (synthesis)	6m 42s
Large Designs Tests / Opentitan parsing (quick)	8m 59s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	9m 7s
Formal Verification Tests / simple	13m 37s
Parsing Tests / SystemVerilog Plugin	30m 54s
Formal Verification Tests / sv2v	19m 9s
Formal Verification Tests / yosys	14m 32s
Parsing Tests / Surelog	21m 52s
Formal Verification Tests / Passlist Check	1m 35s
Parsing Tests / Summary Generation	1m 8s
Parsing Tests / Generate AST diff	0s
Release Package	0s
Release Package Installation Test	0s
	7h 33m 12s

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