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Struct hier path #5326

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Struct hier path

Struct hier path #5326

Triggered via pull request November 28, 2023 06:01
@alaindargelasalaindargelas
synchronize #2166
alaindargelas:struct_hier_path
Status Success
Total duration 1h 25m 5s
Artifacts 22

main.yml

on: pull_request
Matrix: build-binaries
Build sv2v
1m 35s
Build sv2v
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 27s
Style check
Test "Installation from source" from README
52m 22s
Test "Installation from source" from README
Upload GHA event file
4s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
30m 20s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 13s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 15s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
40m 51s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
1h 16m
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 53s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
22m 57s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
1h 11m
Large Designs Tests / Black Parrot (ASIC synthesis)
Parsing Tests  /  Surelog
22m 19s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
9m 7s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Test With Packaged Yosys
1m 56s
Test With Packaged Yosys
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 9s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
1m 5s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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Annotations

4 warnings
Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries Expired
126 MB
binaries-asan Expired
1.01 GB
binaries-debian Expired
126 MB
bp_e_bp_unicore_cfg.edif Expired
128 MB
bsg-logs Expired
85.8 MB
bsg-outputs Expired
6.99 MB
event.json Expired
27.5 KB
formal-verification-logs Expired
623 MB
formal-verification-tests-list Expired
53.6 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired
2.09 MB
lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif Expired
223 MB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit Expired
9.28 MB
opentitan-logs-full Expired
165 MB
opentitan-logs-quick Expired
39.2 MB
parsing_read-systemverilog_logs Expired
14.8 MB
parsing_read-systemverilog_yosys-sv Expired
310 KB
parsing_read-uhdm_logs Expired
14.7 MB
parsing_read-uhdm_yosys-sv Expired
308 KB
parsing_test-results Expired
20.3 KB
plots Expired
23.2 MB
sv2v Expired
8.3 MB
top_artya7.bit Expired
2.09 MB