one more case

tests/simple_tests/MultiDimHierPath4/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/MultiDimHierPath4/dut.sv

@@ -0,0 +1,19 @@
+module dut(
+    input logic clk,
+    input logic [3:0] a,
+    input logic [3:0] b,
+    output logic [1:0][3:0] out
+);
+    typedef logic [3:0] logic4;
+
+    typedef struct packed {
+        logic4 [1:0] vector2x4;
+    } s_t;
+    s_t s;
+
+   assign s.vector2x4[0] = a;
+   assign s.vector2x4[1] = b;
+
+   assign out = s.vector2x4;
+
+endmodule

tests/simple_tests/MultiDimHierPath4/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+sim -clock clk -rstlen 10 -vcd dump.vcd