Package enum const pushing

frontends/systemverilog/uhdm_ast_frontend.cc

@@ -43,8 +43,10 @@ struct UhdmAstFrontend : public UhdmCommonFrontend {
         UHDM::Serializer serializer;
 
         std::vector<vpiHandle> restoredDesigns = serializer.Restore(filename);
+        vpiHandle designH = restoredDesigns.at(0);
+        UHDM::design *design = UhdmDesignFromVpiHandle(designH);
         UHDM::SynthSubset *synthSubset =
-          make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, false);
+          make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, design, false);
         synthSubset->listenDesigns(restoredDesigns);
         delete synthSubset;
         UhdmAst uhdm_ast(this->shared);

frontends/systemverilog/uhdm_surelog_ast_frontend.cc

@@ -201,9 +201,11 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
         // `-defer` turns elaboration off, so check for it
         // Should be called 1. for normal flow 2. after finishing with `-link`
         if (!this->shared.defer) {
+            vpiHandle designH = uhdm_designs.at(0);
+            UHDM::design *design = UhdmDesignFromVpiHandle(designH);
             UHDM::Serializer serializer;
             UHDM::SynthSubset *synthSubset =
-              make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, false);
+              make_new_object_with_optional_extra_true_arg<UHDM::SynthSubset>(&serializer, this->shared.nonSynthesizableObjects, design, false);
             synthSubset->listenDesigns(uhdm_designs);
             delete synthSubset;
         }

tests/formal/passlist.txt

@@ -157,6 +157,7 @@ simple:OneReplicate/dut.v
 simple:OneStruct/dut.sv
 simple:OneSysFunc/dut.v
 simple:PackageCast/dut.v
+simple:PackageEnumConstPush/dut.sv
 simple:PackageLogicTypespec/dut.sv
 simple:PackedArray/top.sv
 simple:PackedArrayPort/top.sv

tests/simple_tests/PackageEnumConstPush/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/PackageEnumConstPush/dut.sv

@@ -0,0 +1,23 @@
+package pkg;
+
+    typedef enum logic {
+        TEST_1,
+        TEST_2
+    } test_t;
+
+    function test_t swap(test_t test);
+        unique case (test)
+            TEST_1: return TEST_2; // works with pkg::TEST_1
+            TEST_2: return TEST_1; // works with pkg::TEST_2
+        endcase
+    endfunction
+
+endpackage
+
+module dut (
+    input logic clk,
+    input  pkg::test_t a,
+    output pkg::test_t b
+);
+    always_comb b = pkg::swap(a);
+endmodule

tests/simple_tests/PackageEnumConstPush/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd