Parameter typespec issue

CMakeLists.txt

@@ -9,7 +9,7 @@ cmake_minimum_required(VERSION 3.20 FATAL_ERROR)
 # can also be installed on the system. This cmake is largely copied from the
 # Surelog cmake
 
-project(SYNLIG VERSION 1.76)
+project(SYNLIG VERSION 1.77)
 
 # Detect build type, fallback to release and throw a warning if use didn't
 # specify any

frontends/systemverilog/uhdm_ast.cc

@@ -1536,6 +1536,13 @@ void UhdmAst::visit_default_expr(vpiHandle obj_h)
     });
 }
 
+void UhdmAst::process_array_expr(const UHDM::BaseClass *object)
+{
+    // Array expr are created in the UHDM elaborated model to model expanded default pattern assigns.
+    // They are not processed so far by the plugin. The plugin processes the non-expanded version in the non-elab model.
+    // Creating a function that is a no-op for now to enable traversing UHDM without error
+}
+
 AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
 {
     s_vpi_value val;
@@ -4054,6 +4061,11 @@ void UhdmAst::process_assignment_pattern_op()
     std::vector<AST::AstNode *> assignments;
     visit_one_to_many({vpiOperand}, obj_h, [&](AST::AstNode *node) {
         if (node->type == AST::AST_ASSIGN || node->type == AST::AST_ASSIGN_EQ || node->type == AST::AST_ASSIGN_LE) {
+            if (assign_node == nullptr) {
+                // Parameter assigns are not assigns per-se, the find_ancestor returns nullptr, but an assign is created in the visit_one_to_many,
+                // selecting this assign for the downstream processing
+                assign_node = node;
+            }
             assignments.push_back(node);
         } else {
             current_node->children.push_back(node);
@@ -4971,6 +4983,11 @@ void UhdmAst::process_parameter()
                         auto it = shared.param_types.find(current_node->str);
                         if (it == shared.param_types.end())
                             shared.param_types.insert(std::make_pair(current_node->str, node->clone()));
+                    } else {
+                        // parameter type
+                        auto it = shared.param_types.find(current_node->str);
+                        if (it == shared.param_types.end())
+                            shared.param_types.insert(std::make_pair(current_node->str, node->clone()));
                     }
                     if (node && node->attributes.count(UhdmAst::packed_ranges())) {
                         for (auto r : node->attributes[UhdmAst::packed_ranges()]->children) {
@@ -5445,6 +5462,9 @@ AST::AstNode *UhdmAst::process_object(vpiHandle obj_handle)
     case vpiClockingBlock:
         process_unsupported_stmt(object);
         break;
+    case vpiArrayExpr:
+        process_array_expr(object);
+        break;
     case vpiTypeParameter:
         process_type_parameter();
         break;

frontends/systemverilog/uhdm_ast.h

@@ -177,6 +177,7 @@ class UhdmAst
     void process_type_parameter();
     void simplify_parameter(::Yosys::AST::AstNode *parameter, ::Yosys::AST::AstNode *module_node = nullptr);
     void process_unsupported_stmt(const UHDM::BaseClass *object, bool is_error = true);
+    void process_array_expr(const UHDM::BaseClass *object);
 
     UhdmAst(UhdmAst *p, UhdmAstShared &s, const std::string &i) : parent(p), shared(s), indent(i)
     {

tests/formal/passlist.txt

@@ -182,6 +182,7 @@ simple:ParameterPassedToSubmoduleInGenscopeOfSubmodule/top.sv
 simple:ParameterPassedToSubmoduleOfSubmodule/top.sv
 simple:ParameterRangeUsingDot/top.sv
 simple:ParameterSizeOfInstance/top.sv
+simple:ParameterType/dut.sv
 simple:ParameterUnpackedArray/top.sv
 simple:ParameterUnpackedLogicArray/top.sv
 simple:ParameterUnsignedInt/top.sv

tests/simple_tests/ParameterType/Makefile.in

@@ -0,0 +1,2 @@
+TEST_FILES := $(TEST_DIR)/dut.sv
+TOP_MODULE := dut

tests/simple_tests/ParameterType/dut.sv

@@ -0,0 +1,6 @@
+
+module dut(input logic clk);
+
+localparam int GW_CONFIG2[2:0] = '{default:0} ;
+
+endmodule

tests/simple_tests/ParameterType/yosys_script.tcl

@@ -0,0 +1,6 @@
+source ../yosys_common.tcl
+
+prep -top \\dut
+write_verilog
+write_verilog yosys.sv
+sim -clock clk -rstlen 10 -vcd dump.vcd