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modified .gitignore to ignore db dir generated from fpga emulation #1010

modified .gitignore to ignore db dir generated from fpga emulation

modified .gitignore to ignore db dir generated from fpga emulation #1010

Triggered via push February 23, 2025 22:52
Status Failure
Total duration 36s
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lint.yml

on: push
Verilog Compilation and Style
28s
Verilog Compilation and Style
Python Style
10s
Python Style
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11 errors
Python Style
Process completed with exit code 1.
Verilog Compilation and Style: lbist/lfsr/lfsr.v#L72
Lines must be no longer than 120 characters.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L27
Provide an explicit type in `parameter` declaration.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L319
Follow keyword with exactly 1 space.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L321
Follow keyword with a colon, newline, or exactly 1 space.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L322
Follow keyword with exactly 1 space.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L339
Follow keyword with exactly 1 space.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L340
Follow keyword with exactly 1 space.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L341
Add an `else` clause to the `if` statement.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L343
Follow keyword with a newline or exactly 1 space.
Verilog Compilation and Style: lbist/lfsr/lfsr_galois.v#L351
Follow keyword with exactly 1 space.