Merge branch 'main' into fft_pysim #558
UnsignedBytelint.yml
on: push
Verilog Compilation and Style
40s
Python Style
9s
Annotations
3 errors and 2 warnings
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Python Style
Process completed with exit code 1.
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Verilog Compilation and Style:
fft/helpers/sine_wave.v#L15
Use `generate`/`endgenerate` keywords to define generate regions.
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Verilog Compilation and Style
Process completed with exit code 2.
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Python Style
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
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Verilog Compilation and Style
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
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