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Cleaned up code
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tomaschoi03 committed Mar 15, 2024
1 parent cdd62bd commit 8b6f7fe
Showing 1 changed file with 0 additions and 28 deletions.
28 changes: 0 additions & 28 deletions src/classifier/classifier.v
Original file line number Diff line number Diff line change
Expand Up @@ -58,20 +58,6 @@ module classifier_Classifier #(
.send_msg(out_mag)
);

// Register for magnitude output
logic [BIT_WIDTH-1:0] out_mag_reg[N_SAMPLES - 1:0];

// arr_ResetReg #(
// .BIT_WIDTH (BIT_WIDTH),
// .RESET_VALUE({BIT_WIDTH{1'b0}}),
// .N_ELEMENTS (N_SAMPLES)
// ) mag_reg (
// .clk(clk),
// .reset(reset),
// .d(out_mag),
// .q(out_mag_reg)
// );

// Filter based on cutoff

logic [BIT_WIDTH-1:0] frequency_array[N_SAMPLES-1:0];
Expand All @@ -97,20 +83,6 @@ module classifier_Classifier #(
.filtered_valid(out_filter)
);

// Register for classify
logic [BIT_WIDTH-1:0] out_highpass_reg[N_SAMPLES - 1:0];

// arr_ResetReg #(
// .BIT_WIDTH (BIT_WIDTH),
// .RESET_VALUE({BIT_WIDTH{1'b0}}),
// .N_ELEMENTS (N_SAMPLES)
// ) highpass_reg (
// .clk(clk),
// .reset(reset),
// .d(out_filter),
// .q(out_highpass_reg)
// );

// Do comparison mag > cutoff_mag
logic out_comparison;
logic comparison_done;
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