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A brainfuck-native soft processor written in Verilog.

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brainfuck_uP

A brainfuck-native soft processor written in Verilog.

The only project included at the moment is the one used for the Brainfuino [-]+. board. It's implemented in a Lattice Diamond project for a MachXO2 FPGA (LCMXO2-640HC-4TG100C).

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The source code is in the source folder.

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Eduardo Corpeño

For bug report or anything related to brainfuck_uP, I may be reached at [email protected]

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A brainfuck-native soft processor written in Verilog.

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