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Tsinghua University
- Beijing,China
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Nontrivial-RISCV
Nontrivial-RISCV PublicA light-weighted fully-pipelined RISC-V CPU with BPU and I-Cache.
SystemVerilog 1
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MipsGreatAgain-Soc
MipsGreatAgain-Soc PublicA light-weighted synthesizable 9-stage-pipelined MIPS processor with branch prediction and CP1(FPU) support.
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