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Quartus/IP/.qsys_edit/flash_interface_10M04SCU169C8G_schematic.nlv
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,14 +1,14 @@ | ||
| # # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 | ||
| # | ||
| preplace inst flash_interface_10M04SCU169C8G.clk_source -pg 1 -lvl 1 -y 30 | ||
| preplace inst flash_interface_10M04SCU169C8G.avalon_bridge -pg 1 -lvl 2 -y 70 | ||
| preplace inst flash_interface_10M04SCU169C8G.clk_source -pg 1 -lvl 1 -y 50 | ||
| preplace inst flash_interface_10M04SCU169C8G.avalon_bridge -pg 1 -lvl 2 -y 90 | ||
| preplace inst flash_interface_10M04SCU169C8G -pg 1 -lvl 1 -y 40 -regy -20 | ||
| preplace inst flash_interface_10M04SCU169C8G.onchip_flash -pg 1 -lvl 3 -y 50 | ||
| preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)clk_source.clk,(SLAVE)avalon_bridge.clk,(SLAVE)onchip_flash.clk) 1 1 2 330 60 N | ||
| preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)avalon_bridge.avalon_master,(SLAVE)onchip_flash.data,(SLAVE)onchip_flash.csr) 1 2 1 580 | ||
| preplace inst flash_interface_10M04SCU169C8G.onchip_flash -pg 1 -lvl 3 -y 70 | ||
| preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)clk_source.clk_in,(SLAVE)flash_interface_10M04SCU169C8G.clk) 1 0 1 NJ | ||
| preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)clk_source.clk_reset,(SLAVE)avalon_bridge.reset,(SLAVE)onchip_flash.nreset) 1 1 2 310 180 620 | ||
| preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)flash_interface_10M04SCU169C8G.reset,(SLAVE)clk_source.clk_in_reset) 1 0 1 NJ | ||
| preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.reset,(MASTER)clk_source.clk_reset,(SLAVE)onchip_flash.nreset) 1 1 2 310 160 580 | ||
| preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.external_interface,(SLAVE)flash_interface_10M04SCU169C8G.external_interface) 1 0 2 NJ 100 NJ | ||
| levelinfo -pg 1 0 110 710 | ||
| levelinfo -hier flash_interface_10M04SCU169C8G 120 150 360 610 700 | ||
| preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.clk,(SLAVE)onchip_flash.clk,(MASTER)clk_source.clk) 1 1 2 330 200 600 | ||
| preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.external_interface,(SLAVE)flash_interface_10M04SCU169C8G.external_interface) 1 0 2 NJ 40 NJ | ||
| preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)avalon_bridge.avalon_master,(SLAVE)onchip_flash.csr,(SLAVE)onchip_flash.data) 1 2 1 620 | ||
| levelinfo -pg 1 0 110 750 | ||
| levelinfo -hier flash_interface_10M04SCU169C8G 120 150 380 650 740 |
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109 changes: 109 additions & 0 deletions
109
Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.spd
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| @@ -0,0 +1,109 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <simPackage> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="error_adapter_0" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v" | ||
| type="VERILOG" | ||
| library="avalon_st_adapter" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="rsp_mux" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_arbitrator.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="rsp_mux" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="rsp_demux" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="cmd_mux" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_arbitrator.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="cmd_mux" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="cmd_demux" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="router_001" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="router" /> | ||
| <file | ||
| path="simulation/submodules/altera_avalon_sc_fifo.v" | ||
| type="VERILOG" | ||
| library="onchip_flash_csr_agent_rsp_fifo" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_slave_agent.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="onchip_flash_csr_agent" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_burst_uncompressor.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="onchip_flash_csr_agent" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_master_agent.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="avalon_bridge_avalon_master_agent" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_slave_translator.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="onchip_flash_csr_translator" /> | ||
| <file | ||
| path="simulation/submodules/altera_merlin_master_translator.sv" | ||
| type="SYSTEM_VERILOG" | ||
| library="avalon_bridge_avalon_master_translator" /> | ||
| <file | ||
| path="simulation/submodules/altera_reset_controller.v" | ||
| type="VERILOG" | ||
| library="rst_controller" /> | ||
| <file | ||
| path="simulation/submodules/altera_reset_synchronizer.v" | ||
| type="VERILOG" | ||
| library="rst_controller" /> | ||
| <file | ||
| path="simulation/submodules/altera_reset_controller.sdc" | ||
| type="SDC" | ||
| library="rst_controller" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v" | ||
| type="VERILOG" | ||
| library="mm_interconnect_0" /> | ||
| <file | ||
| path="simulation/submodules/altera_onchip_flash_util.v" | ||
| type="VERILOG" | ||
| library="onchip_flash" /> | ||
| <file | ||
| path="simulation/submodules/altera_onchip_flash.v" | ||
| type="VERILOG" | ||
| library="onchip_flash" /> | ||
| <file | ||
| path="simulation/submodules/altera_onchip_flash_avmm_data_controller.v" | ||
| type="VERILOG" | ||
| library="onchip_flash" /> | ||
| <file | ||
| path="simulation/submodules/altera_onchip_flash_avmm_csr_controller.v" | ||
| type="VERILOG" | ||
| library="onchip_flash" /> | ||
| <file | ||
| path="simulation/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v" | ||
| type="VERILOG" | ||
| library="avalon_bridge" /> | ||
| <file path="simulation/flash_interface_10M04SCU169C8G.v" type="VERILOG" /> | ||
| <topLevel name="flash_interface_10M04SCU169C8G" /> | ||
| <deviceFamily name="max10" /> | ||
| <modelMap | ||
| controllerPath="flash_interface_10M04SCU169C8G.onchip_flash" | ||
| modelPath="flash_interface_10M04SCU169C8G.onchip_flash" /> | ||
| </simPackage> |
50 changes: 50 additions & 0 deletions
50
Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation.rpt
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40 changes: 40 additions & 0 deletions
40
.../IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation_previous.rpt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| Info: Starting: Create HDL design files for synthesis | ||
| Info: qsys-generate C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G.qsys --synthesis=VERILOG --output-directory=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G\synthesis --family="MAX 10" --part=10M04SCU169C8G | ||
| Progress: Loading IP/flash_interface_10M04SCU169C8G.qsys | ||
| Progress: Reading input file | ||
| Progress: Adding avalon_bridge [altera_up_external_bus_to_avalon_bridge 18.0] | ||
| Progress: Parameterizing module avalon_bridge | ||
| Progress: Adding clk_source [clock_source 22.1] | ||
| Progress: Parameterizing module clk_source | ||
| Progress: Adding onchip_flash [altera_onchip_flash 22.1] | ||
| Progress: Parameterizing module onchip_flash | ||
| Progress: Building connections | ||
| Progress: Parameterizing connections | ||
| Progress: Validating | ||
| Progress: Done reading input file | ||
| Info: flash_interface_10M04SCU169C8G: Generating flash_interface_10M04SCU169C8G "flash_interface_10M04SCU169C8G" for QUARTUS_SYNTH | ||
| Info: avalon_bridge: Starting Generation of External Bus to Avalon Bridge | ||
| Info: avalon_bridge: "flash_interface_10M04SCU169C8G" instantiated altera_up_external_bus_to_avalon_bridge "avalon_bridge" | ||
| Info: onchip_flash: Generating top-level entity altera_onchip_flash | ||
| Info: onchip_flash: "flash_interface_10M04SCU169C8G" instantiated altera_onchip_flash "onchip_flash" | ||
| Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 | ||
| Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 | ||
| Info: mm_interconnect_0: "flash_interface_10M04SCU169C8G" instantiated altera_mm_interconnect "mm_interconnect_0" | ||
| Info: rst_controller: "flash_interface_10M04SCU169C8G" instantiated altera_reset_controller "rst_controller" | ||
| Info: avalon_bridge_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "avalon_bridge_avalon_master_translator" | ||
| Info: onchip_flash_csr_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "onchip_flash_csr_translator" | ||
| Info: avalon_bridge_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "avalon_bridge_avalon_master_agent" | ||
| Info: onchip_flash_csr_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "onchip_flash_csr_agent" | ||
| Info: onchip_flash_csr_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "onchip_flash_csr_agent_rsp_fifo" | ||
| Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" | ||
| Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" | ||
| Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" | ||
| Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" | ||
| Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" | ||
| Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" | ||
| Info: Reusing file C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/submodules/altera_merlin_arbitrator.sv | ||
| Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" | ||
| Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" | ||
| Info: flash_interface_10M04SCU169C8G: Done "flash_interface_10M04SCU169C8G" with 18 modules, 27 files | ||
| Info: qsys-generate succeeded. | ||
| Info: Finished: Create HDL design files for synthesis |
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