v1.0.4 PRODUCTION

Major New Features:

• [TS-8152] Assigned Rev 0x0A Output pins as follows:
  OUT0P and OUT0N: frequency range output_freq_range_ptp and and esync range freq_range_esync
  OUT1P and OUT1N: fixed to 10 MHz and ePPS On
  OUT2P and OUT2N: fixed to 10 MHz and ePPS On
  OUT3P and OUT3N: fixed to 156.25 MHz and ePPS Off
  OUT4P and OUT4N: fixed to 156.25 MHz and ePPS Off
  OUT5P and OUT5N: fixed to 156.25 MHz and ePPS Off
  OUT6P and OUT6N: fixed to 1 Hz and ePPS Off
  OUT7P and OUT7N: fixed to 1 Hz and ePPS Off
  OUT8P and OUT8N: frequency range output_freq_range_ptp and esync range freq_range_esync
  OUT9P and OUT9N - fixed to 25 MHz and ePPS Off.

New Features:

• [TS-8190] Added an output frequency assignment table to the MD documentation file.

• [TS-8192] Added a new kconfig define 'CONFIG_ZL3073X_MFG_FILE_AVAILABLE' to enable/disable the local DPLL configuration.

Major Bug Fixes:

• None

Bug Fixes:

• None

Other Notes:

• [TS-8112] Updated coding style issues for Azurite PHC.

• [TS-8156] Changed Rev 0x0A input and output pin names

        input_pin_names
  
        REF0P: 1PPS_IN1
        REF0N: 1PPS_IN0
        REF1P: RCLKA_IN
        REF1N: RCLKB_IN
        REF2P: REF2P
        REF2N: GNSS_10M_IN
        REF3P: SMA1_IN
        REF3N: SMA3_IN
        REF4P: GNSS_1PPS_IN
        REF4N: REF4N
  
        output_pin_names
  
        OUT0P: SMA0_OUT
        OUT0N: 1PPS_OUT4
        OUT1P: OUT1P
        OUT1N: AIC_SCLK
        OUT2P: AIC_SCLK2
        OUT2N: SMA2_OUT
        OUT3P: SYNC_CLK1_P
        OUT3N: SYNC_CLK1_N
        OUT4P: SYNC_CLK0_P
        OUT4N: SYNC_CLK0_N
        OUT5P: SYNC_CLK2_P
        OUT5N: SYNC_CLK2_N
        OUT6P: 1Hz_FREQ
        OUT6N: SYNC_CLK_GD
        OUT7P: 1PPS_OUT3
        OUT7N: 1PPS_OUT2
        OUT8P: 1PPS_OUT1
        OUT8N: 1PPS_OUT0
        OUT9P: SYNC_25M_P
        OUT9N: SYNC_25M_N.
  

---

What's Changed

• Release ptp4 l 1.0.4 upload by @nss1588 in #9

Full Changelog: v1.0.2...v1.0.4

v1.0.2-eng

Major New Features:

• None

New Features:

• None

Major Bug Fixes:

• [TS-8144] Fixed order of operation in zl3073x_dpll_phase_offset_get(). Phase offset measurements from references that were not locked to the dpll
  were returning 0 even though they qualify.

Bug Fixes:

• None

Other Notes:

• [TS-8141] Removed checkpatch Linux warnings.

What's Changed

• TS-8141 phc fix remaining checkpatch.pl warnings by @nss1588 in #7

Full Changelog: v1.0.0...v1.0.2

v1.0.0-eng

v1.0.0 is the first Azurite Linux PHC and DPLL manager Engineering release.

New Features

• [TS-7823] Added new functions zl80732_ptp_adjphase() and zl80732_ptp_getmaxphase().

• [TS-8035] Added support for the dpll_pin_ops and the dpll_device_ops interfaces. Added defines ZL3073X_DPLL_NETLINK_ENABLED and ZL3073X_PHC_ENABLED
  to zl3073x_probe().

• [TS-8036] Added zl3073x_dpll_raw_mode_get() function to get the DPLL mode.

• [TS-8037] Added zl3073x_dpll_lock_status_get() and
  zl3073x_dpll_map_raw_to_manager_lock_status() functions.

• [TS-8038] Added function zl3073x_dpll_pin_state_on_dpll_get() to implement state_on_dpll_get() from the dpll_pin_ops interface.

• [TS-8040] Added function zl3073x_dpll_pin_direction_get() to implement direction_get() from the dpll_pin_ops interface.

• [TS-8041] added
  zl3073x_dpll_get_priority_ref() and zl3073x_dpll_set_priority_ref().

• [TS-8044] Added function zl3073x_dpll_pin_phase_offset_get() to implement phase_offset_get() from the dpll_pin_ops interface.

• [TS-8046] Added function zl3073x_dpll_pin_ffo_get() to implement ffo_get() from the dpll_pin_ops interface.

• [TS-8047] Added the following functions to implement esync_get() and esync_set() from the dpll_pin_ops interface:
  zl3073x_dpll_input_pin_esync_get()
  zl3073x_dpll_input_pin_esync_set()
  zl3073x_dpll_output_pin_esync_get()
  zl3073x_dpll_output_pin_esync_set().

Other Minor Changes

• [TS-7825] Added zl80732_dpll_init_fine_phase_adjust() to fix firmware bug generating wrong synthesizer cycle.

• [TS-7899] Updated zl80732_ptp_adjtime() to apply the entire provided offset, and fixed issue with the ToD register updates.

• [TS-8070] Added zl3073x_dpll_get_input_frequency() and zl3073x_dpll_set_input_frequency for DPLL manager.

• [TS-8073] Added zl3073x_dpll_get_output_phase_adjust() and zl3073x_dpll_set_output_phase_adjust() functions for DPLL manager.

• [TS-8101] Changed handling of error status of zl3073x_read() and zl3073x_write().

• [TS-8127] Added dpll_pin_change_ntf() and dpll_device_change_ntf() to support DPLL subsystem notification.

• [TS-8129] Split dpll_pin_ops into separate interfaces for inputs and outputs.

• [TS-8139] Added board config defines CONFIG_MD_990_0011_REV_8 and CONFIG_MD_990_0011_REV_A.

---

Full Changelog: https://github.com/microchip-ung/tcg-phc-dpll/commits/v1.0.0