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    27 repositories

    • Digital-Logic-Design

      Public
      透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
      fpgadigitalvhdlveriloglearnxilinxdigital-logicsystemveriloghdlverilog-hdl
      Verilog
      •
      Other
      •4•15•0•0•Updated Oct 25, 2023Oct 25, 2023

    • mp3_converter

      Public
      Python browser automation for mp3' downloads from you tube
      Python
      •
      GNU General Public License v3.0
      •2•0•0•0•Updated Jan 11, 2023Jan 11, 2023

    • ghdl

      Public
      VHDL 2008/93/87 simulator
      VHDL
      •
      GNU General Public License v2.0
      •366•0•0•0•Updated Nov 8, 2022Nov 8, 2022

    • slang

      Public
      SystemVerilog compiler and language services
      C++
      •
      MIT License
      •141•0•0•0•Updated Nov 8, 2022Nov 8, 2022

    • myhdl

      Public
      The MyHDL development repository
      Python
      •
      GNU Lesser General Public License v2.1
      •248•0•0•0•Updated Nov 4, 2022Nov 4, 2022

    • nextpnr

      Public
      nextpnr portable FPGA place and route tool
      C++
      •
      ISC License
      •245•0•0•0•Updated Oct 30, 2022Oct 30, 2022

    • e203_hbirdv2

      Public
      The Ultra-Low Power RISC-V Core
      Verilog
      •
      Apache License 2.0
      •346•0•0•0•Updated Oct 27, 2022Oct 27, 2022

    • FPGA-USB-Device

      Public
      An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
      SystemVerilog
      •106•0•0•0•Updated Oct 25, 2022Oct 25, 2022

    • prjtrellis

      Public
      Documenting the Lattice ECP5 bit-stream format.
      Python
      •
      Other
      •87•0•0•0•Updated Oct 12, 2022Oct 12, 2022

    • icestorm

      Public
      Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
      Python
      •
      ISC License
      •224•0•0•0•Updated Oct 1, 2022Oct 1, 2022

    • pp4fpgas

      Public
      Parallel Programming for FPGAs -- An open-source high-level synthesis book
      TeX
      •
      Creative Commons Attribution 4.0 International
      •149•0•0•0•Updated Apr 22, 2022Apr 22, 2022

    • Verilog-FixedPoint

      Public
      A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
      SystemVerilog
      •25•0•0•0•Updated Apr 17, 2022Apr 17, 2022

    • BSV_Tutorial_cn

      Public
      一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
      Bluespec
      •
      MIT License
      •43•0•0•0•Updated Mar 11, 2022Mar 11, 2022

    • wavedrom.github.io

      Public
      Digital timing diagram editor
      JavaScript
      •
      MIT License
      •162•0•0•0•Updated Feb 26, 2022Feb 26, 2022

    • hbird-sdk

      Public
      OpenSource HummingBird RISC-V Software Development Kit
      C
      •
      Apache License 2.0
      •49•0•0•0•Updated Jan 17, 2022Jan 17, 2022

    • pint_iverilog

      Public
      Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.
      C++
      •
      GNU Lesser General Public License v2.1
      •2•0•0•0•Updated Nov 15, 2021Nov 15, 2021

    • Multimedia-DataBase

      Public
      Python
      •
      MIT License
      •1•0•0•0•Updated May 21, 2021May 21, 2021

    • multimediainfo

      Public
      forked from laodifang/MediaInfo, Wolcome Pull Requests.
      Python
      •
      MIT License
      •2•0•1•5•Updated May 19, 2021May 19, 2021

    • linter-veriloghdl

      Public
      Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.
      CoffeeScript
      •
      MIT License
      •2•0•0•0•Updated May 15, 2021May 15, 2021

    • e200_opensource

      Public
      Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
      Verilog
      •
      Apache License 2.0
      •1k•0•0•0•Updated Mar 24, 2021Mar 24, 2021

    • hbird-e-sdk

      Public
      Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
      C
      •
      Other
      •85•0•0•0•Updated Mar 24, 2021Mar 24, 2021

    • Python-Instruction-Set-Computer

      Public
      「Python指令集處理器」(Python instruction set computer)是一個基於Python程式語言所製作出的高階指令集處理器，目的是使用邏輯閘的方式組成Python程式，讓處理器在運作的時候可以如Python一樣的簡潔、快速。
      cpufpgacomputerveriloghdlinstruction-setinstructionpython-instruction-setinstruction-set-computerpython
      MIT License
      •0•0•7•0•Updated Nov 17, 2020Nov 17, 2020

    • RISC-V-Single-Cycle-CPU

      Public
      A RISC-V 32bit single-cycle CPU written in Logisim
      Python
      •44•0•0•0•Updated Sep 2, 2020Sep 2, 2020

    • Multimedia-Processing-Description-Language

      Public
      「多媒體處理描述語言」(MPDL, Multimedia Processing Description Language)是將一部影片如何經由素材、製作流程與後製三項元素融合製作而成，但以程式腳本的方式描述一部影片的製作方式。
      devopsagilemultimediacicdmpdl
      MIT License
      •1•0•3•0•Updated Apr 28, 2020Apr 28, 2020

    • Multimedia-Processing-Description-Language-Server

      Public
      MIT License
      •1•0•0•0•Updated Sep 11, 2019Sep 11, 2019

    • Multimedia-Processing-Description-Language-Editor

      Public
      針對開源項目「多媒體處理描述語言」(Multimedia Processing Description Language)所製作出來的編輯器，並搭配Git版本管理、機器學習、人工智慧、多人協作、自動處理等特性與目標開創新的影片製作流程。
      MIT License
      •1•0•3•0•Updated Sep 11, 2019Sep 11, 2019

    • arachne-pnr

      Public
      Place and route tool for FPGAs
      C++
      •
      MIT License
      •72•0•0•0•Updated Jul 28, 2019Jul 28, 2019