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drm/vc4: hvs: Defer updating the enable_bg_fill until vblank #6463

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merged 1 commit into from
Nov 19, 2024
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drm/vc4: hvs: Defer updating the enable_bg_fill until vblank #6463

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2 changes: 2 additions & 0 deletions drivers/gpu/drm/vc4/vc4_drv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -365,6 +365,8 @@ struct vc4_hvs {
unsigned int enabled: 1;
} eof_irq[HVS_NUM_CHANNELS];

bool bg_fill[HVS_NUM_CHANNELS];

unsigned long max_core_rate;

/* Memory manager for CRTCs to allocate space in the display
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18 changes: 10 additions & 8 deletions drivers/gpu/drm/vc4/vc4_hvs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1509,14 +1509,7 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
/* This sets a black background color fill, as is the case
* with other DRM drivers.
*/
if (enable_bg_fill)
HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
HVS_READ(SCALER6_DISPX_CTRL1(channel)) |
SCALER6(DISPX_CTRL1_BGENB));
else
HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
HVS_READ(SCALER6_DISPX_CTRL1(channel)) &
~SCALER6(DISPX_CTRL1_BGENB));
hvs->bg_fill[channel] = enable_bg_fill;
} else {
/* we can actually run with a lower core clock when background
* fill is enabled on VC4_GEN_5 so leave it enabled always.
Expand Down Expand Up @@ -1700,6 +1693,15 @@ static irqreturn_t vc6_hvs_eof_irq_handler(int irq, void *data)
if (hvs->eof_irq[i].desc != irq)
continue;

if (hvs->bg_fill[i])
HVS_WRITE(SCALER6_DISPX_CTRL1(i),
HVS_READ(SCALER6_DISPX_CTRL1(i)) |
SCALER6(DISPX_CTRL1_BGENB));
else
HVS_WRITE(SCALER6_DISPX_CTRL1(i),
HVS_READ(SCALER6_DISPX_CTRL1(i)) &
~SCALER6(DISPX_CTRL1_BGENB));

vc4_hvs_schedule_dlist_sweep(hvs, i);
return IRQ_HANDLED;
}
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