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rizinorg · Nov 27, 2024 · c4c0c28 · c4c0c28
1 parent a3bf571
commit c4c0c28
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Showing 2 changed files with 34 additions and 0 deletions.
diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -23,6 +23,7 @@ static const char *eps_tbl[] = {
 #define IEPS(I)     VARG(eps_tbl[I])
 
 #define ABS(X) ITE(SGT(X, S32(0)), X, NEG(X))
+#define V32(X) UNSIGNED(32, (X))
 
 typedef RzAnalysisLiftedILOp (*fn_analyze_op_il)(XtensaContext *ctx);
 typedef RzILOpPure *(fn_op2)(RzILOpBool *x, RzILOpBool *y);
@@ -1227,6 +1228,31 @@ static RzAnalysisLiftedILOp op_ssip(XtensaContext *ctx) {
 		SETG(REGN(1), U32(IMM(2))));
 }
 
+static RzAnalysisLiftedILOp op_ssl(XtensaContext *ctx) {
+	return SEQ2(
+		SETL("sa", UNSIGNED(5, IREG(0))),
+		SETG("sar", SUB(U32(32), V32(VARL("sa")))));
+}
+
+static RzAnalysisLiftedILOp op_ssr(XtensaContext *ctx) {
+	return SEQ2(
+		SETL("sa", UNSIGNED(5, IREG(0))),
+		SETG("sar", V32(VARL("sa"))));
+}
+
+static RzAnalysisLiftedILOp op_ssx(XtensaContext *ctx) {
+	return SEQ2(
+		SETL("vAddr", ADD(IREG(1), IREG(2))),
+		STOREW(VARL("vAddr"), V32(IREG(0))));
+}
+
+static RzAnalysisLiftedILOp op_ssxp(XtensaContext *ctx) {
+	return SEQ3(
+		SETL("vAddr", IREG(1)),
+		STOREW(VARL("vAddr"), V32(IREG(0))),
+		SETG(REGN(1), ADD(VARL("vAddr"), IREG(2))));
+}
+
 #include <rz_il/rz_il_opbuilder_end.h>
 
 static const fn_analyze_op_il fn_tbl[] = {
@@ -1497,6 +1523,10 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_SSAI] = op_ssai,
 	[XTENSA_INS_SSI] = op_ssi,
 	[XTENSA_INS_SSIP] = op_ssip,
+	[XTENSA_INS_SSL] = op_ssl,
+	[XTENSA_INS_SSR] = op_ssr,
+	[XTENSA_INS_SSX] = op_ssx,
+	[XTENSA_INS_SSXP] = op_ssxp,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -266,3 +266,7 @@ d "ssai 1" 004140 0x0 (set sar (bv 32 0x1))
 d "ssa8l a1" 002140 0x0 (set sar (<< (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3) false))
 d "ssip f1, a2, 0x3fc" 13c2ff 0x0 (seq (set vAddr (var a2)) (storew 0 (var vAddr) (var f1)) (set a2 (bv 32 0x3fc)))
 d "ssi f1, a2, 0x3fc" 1342ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x3fc))) (storew 0 (var vAddr) (cast 32 false (var f1))))
+d "ssxp f2, a3, a1" 102358 0x0 (seq (set vAddr (var a3)) (storew 0 (var vAddr) (cast 32 false (var f2))) (set a3 (+ (var vAddr) (var a1))))
+d "ssx f2, a3, a1" 102348 0x0 (seq (set vAddr (+ (var a3) (var a1))) (storew 0 (var vAddr) (cast 32 false (var f2))))
+d "ssr a1" 000140 0x0 (seq (set sa (cast 5 false (var a1))) (set sar (cast 32 false (var sa))))
+d "ssl a1" 001140 0x0 (seq (set sa (cast 5 false (var a1))) (set sar (- (bv 32 0x20) (cast 32 false (var sa)))))