[rtl] use past SDA in twd FSM transition

[LukasP46]

Since the SDA has to have a valid value only during high SCL, I had the case where with the fall of SCL the SDA also changed and thus a wrong state transition happened. But the protocol should guarantee a valid input during high SCL, so this should be a valid fix?

The image shows such a transition, which would fail with the old implementation.

[stnolting]

You are right. SDA gets tested here on the falling edge of SCL which is not compliant to the spec (I think)...

However, checking smp.sda_sreg(2) might not be a good idea as this represents the state of SDA from one (processor clock!) cycle before.

[stnolting]

I've modified your PR so that ACK/NACK gets sampled on the rising edge of SCL, but evaluated at the falling edge of SCL (= the end of the ACK/NACK bit phase). This seems to look good - at least with my very simplem test case.

Feel free to revert my changes if this does not work for your test case.

Could you then please provide a minimal test case to reproduce this ACK "race condition"?

[LukasP46]

However, checking smp.sda_sreg(2) might not be a good idea as this represents the state of SDA from one (processor clock!) cycle before.

Spec wise this would be fine "The data on the SDA line must be stable during the HIGH period of the clock." (3.1.3 UM10204
I2C-bus specification and user manual) and even one clock period before the fall should be fine.

But it is not so transparent because it depends on the system clock. So your solution is cleaner and only costs one more bit on the ctrl register...

Feel free to revert my changes if this does not work for your test case.

Works just fine, thanks a lot!

Could you then please provide a minimal test case to reproduce this ACK "race condition"?

Unfortunately I use parts of a library I cannot share, but the tricky part was that the SDA has a transition to '1' at the very same moment the SCL falls.

[LukasP46]

Unfortunately I use parts of a library I cannot share, but the tricky part was that the SDA has a transition to '1' at the very same moment the SCL falls.

Content wise I only read two bytes, so

1. I send the device ID
2. then I read one byte
3. send an ACK (here was the error)
4. then I read one byte and
5. then I don't send an ACK
6. but a stop after the ACK check period.

"I" is the I2C Host which just uses the Testbench TWD ports.

[stnolting]

Spec wise this would be fine "The data on the SDA line must be stable during the HIGH period of the clock." (3.1.3 UM10204 I2C-bus specification and user manual) and even one clock period before the fall should be fine.

This should be the case now.

Works just fine, thanks a lot!

Great to hear! Thank you for testing!