Update makefile scripts

Makefile

@@ -0,0 +1,7 @@
+all: rfsoc2x2 zcu111
+
+rfsoc2x2:
+	$(MAKE) -C boards/RFSoC2x2/rfsoc_radio/
+
+zcu111:
+	$(MAKE) -C boards/ZCU111/rfsoc_radio/

README.md

@@ -53,9 +53,8 @@ cd /<repository-location>/boards/<board-name>/rfsoc_radio/
 Now that we have moved into the correct directory, make the Vivado project by running the make commands below sequentially.
 
 ```sh
-make project
 make block_design
-make bitstream_file
+make bitstream
 ```
 
 Alternatively, you can run the entire project build by executing the following into the tcl console:

boards/RFSoC2x2/rfsoc_radio/Makefile

@@ -1,13 +1,10 @@
-overlay_name := rfsoc_radio
-design_name := block_design
-
-all: project block_design bitstream_file
-
-project:
-	vivado -mode batch -source make_project.tcl -notrace
+all: block_design bitstream clean
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
-bitstream_file:
-	vivado -mode batch -source make_bitstream.tcl -notrace
+bitstream:
+	vivado -mode batch -source make_bitstream.tcl -notrace
+
+clean:
+	rm -rf block_design *.jou *.log NA .Xil

boards/RFSoC2x2/rfsoc_radio/make_bitstream.tcl

@@ -1,5 +1,5 @@
-set overlay_name "rfsoc_radio"
-set design_name "block_design"
+set overlay_name "block_design"
+set design_name "rfsoc_radio"
 
 # Open project
 open_project ./${overlay_name}/${overlay_name}.xpr
@@ -12,11 +12,11 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 4
+launch_runs impl_1 -to_step write_bitstream -jobs 12
 wait_on_run impl_1
 
 # Move and rename bitstream to final location
-file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./bitstream/${overlay_name}.bit
+file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./bitstream/${design_name}.bit
 
 # copy hwh files
-file copy -force ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${design_name}/hw_handoff/${design_name}.hwh ./bitstream/${overlay_name}.hwh
+file copy -force ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${design_name}/hw_handoff/${design_name}.hwh ./bitstream/${design_name}.hwh

boards/RFSoC2x2/rfsoc_radio/make_block_design.tcl

@@ -1,8 +1,17 @@
-set overlay_name "rfsoc_radio"
-set design_name "block_design"
+set overlay_name "block_design"
+set design_name "rfsoc_radio"
+set iprepo_dir ./../../ip/iprepo
 
-# Open project
-open_project ./${overlay_name}/${overlay_name}.xpr
+# Create project
+create_project ${overlay_name} ./${overlay_name} -part xczu28dr-ffvg1517-2-e
+set_property target_language VHDL [current_project]
+
+# Set IP repository paths
+set_property ip_repo_paths $iprepo_dir [current_project]
+update_ip_catalog
+
+# Add constraints
+add_files -fileset constrs_1 -norecurse ./constraints.xdc
 
 # Make block design
-source ./${design_name}.tcl
+source ./${design_name}.tcl

boards/RFSoC2x2/rfsoc_radio/block_design.tcl → boards/RFSoC2x2/rfsoc_radio/rfsoc_radio.tcl

@@ -49,7 +49,7 @@ if { $list_projs eq "" } {
 
 # CHANGE DESIGN NAME HERE
 variable design_name
-set design_name block_design
+set design_name rfsoc_radio
 
 # If you do not already have an existing IP Integrator design open,
 # you can create a design using the following command:

boards/ZCU111/rfsoc_radio/Makefile

@@ -1,13 +1,10 @@
-overlay_name := rfsoc_radio
-design_name := block_design
-
-all: project block_design bitstream_file
-
-project:
-	vivado -mode batch -source make_project.tcl -notrace
+all: block_design bitstream clean
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
-bitstream_file:
-	vivado -mode batch -source make_bitstream.tcl -notrace
+bitstream:
+	vivado -mode batch -source make_bitstream.tcl -notrace
+
+clean:
+	rm -rf block_design *.jou *.log NA .Xil

boards/ZCU111/rfsoc_radio/make_bitstream.tcl

@@ -1,5 +1,5 @@
-set overlay_name "rfsoc_radio"
-set design_name "block_design"
+set overlay_name "block_design"
+set design_name "rfsoc_radio"
 
 # Open project
 open_project ./${overlay_name}/${overlay_name}.xpr
@@ -12,11 +12,11 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 4
+launch_runs impl_1 -to_step write_bitstream -jobs 12
 wait_on_run impl_1
 
 # Move and rename bitstream to final location
-file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./bitstream/${overlay_name}.bit
+file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./bitstream/${design_name}.bit
 
 # copy hwh files
-file copy -force ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${design_name}/hw_handoff/${design_name}.hwh ./bitstream/${overlay_name}.hwh
+file copy -force ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${design_name}/hw_handoff/${design_name}.hwh ./bitstream/${design_name}.hwh

boards/ZCU111/rfsoc_radio/make_block_design.tcl

@@ -1,8 +1,17 @@
-set overlay_name "rfsoc_radio"
-set design_name "block_design"
+set overlay_name "block_design"
+set design_name "rfsoc_radio"
+set iprepo_dir ./../../ip/iprepo
 
-# Open project
-open_project ./${overlay_name}/${overlay_name}.xpr
+# Create project
+create_project ${overlay_name} ./${overlay_name} -part xczu28dr-ffvg1517-2-e
+set_property target_language VHDL [current_project]
+
+# Set IP repository paths
+set_property ip_repo_paths $iprepo_dir [current_project]
+update_ip_catalog
+
+# Add constraints
+add_files -fileset constrs_1 -norecurse ./constraints.xdc
 
 # Make block design
-source ./${design_name}.tcl
+source ./${design_name}.tcl