Separate xbar and replace en/rdy with val/rdy #181
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| # This workflow will install Python dependencies, run tests and lint with a variety of Python versions | |
| # For more information see: https://docs.github.com/en/actions/automating-builds-and-tests/building-and-testing-python | |
| name: Python package | |
| on: | |
| push: | |
| branches: [ "master" ] | |
| pull_request: | |
| branches: [ "master" ] | |
| jobs: | |
| build: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| python-version: ["3.7.13", "3.9.20", "3.12.8"] | |
| steps: | |
| - uses: actions/checkout@v3 | |
| with: | |
| submodules: true | |
| - name: Set up Python ${{ matrix.python-version }} | |
| uses: actions/setup-python@v3 | |
| with: | |
| python-version: ${{ matrix.python-version }} | |
| - name: Install Verilator | |
| run: | | |
| wget https://github.com/tancheng/pymtl-verilator/raw/master/verilator-travis-4.036.tar.gz | |
| tar -C ${HOME} -xzf verilator-travis-4.036.tar.gz | |
| echo "VERILATOR_ROOT=${HOME}/verilator" >> $GITHUB_ENV | |
| echo "PYMTL_VERILATOR_INCLUDE_DIR=${HOME}/verilator/share/verilator/include" >> $GITHUB_ENV | |
| echo "${HOME}/verilator/bin" >> $GITHUB_PATH | |
| - name: Check Verilator | |
| run: | | |
| echo ${VERILATOR_ROOT} | |
| echo ${PYMTL_VERILATOR_INCLUDE_DIR} | |
| verilator --version | |
| - name: Install dependencies | |
| run: | | |
| sudo apt-get install -y graphviz | |
| sudo apt-get install git libffi-dev | |
| python3 -m venv ${HOME}/venv | |
| source ${HOME}/venv/bin/activate | |
| pip install py==1.11.0 | |
| pip install wheel | |
| pip install -U git+https://github.com/tancheng/pymtl3.1@yo-struct-list-fix | |
| pip install hypothesis | |
| pip install pytest | |
| pip list | |
| - name: Test and translate with pytest | |
| run: | | |
| mkdir -p build && cd build | |
| source ${HOME}/venv/bin/activate | |
| # Simulation across all tests. | |
| pytest .. -v | |
| # Tile translation. | |
| pytest ../tile/test/TileSeparateCrossbarRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd | |
| # CGRA template translation. | |
| pytest ../cgra/test/CgraTemplateRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd | |
| # TODO: Need to check vector/heterogneous modules exist in the generated Verilog. | |
| # CGRA simulation/translation (including heterogeneous, kingmesh, vector). | |
| pytest ../cgra/test/CgraCrossbarDataMemRingCtrlMemRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd | |
| # 3x3 CGRA performs 2x2 matmul simulation/translation. | |
| pytest ../systolic/test/Cgra3x3MemRightAndBottomRTL_matmul_2x2_test.py -xvs --test-verilog --dump-vtb --dump-vcd | |
| # Ring network simulation. | |
| pytest ../noc/PyOCN/pymtl3_net/ringnet/test/RingNetworkRTL_test.py | |
| # CGRAs are interconnected with ring topology. The CGRA contains | |
| # separate crossbars (for tiles and FUs), crossbar-based data memory (for | |
| # multi-bank), and controller. | |
| pytest ../scale_out/test/RingMultiCgraRingCtrlMemRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd | |