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[P2] Support multi-cycle custom FU
new feature
New feature or request
#57
opened Jan 4, 2025 by
tancheng
[P2] Support prologue and epilogue for ctrl memory engine
new feature
New feature or request
#55
opened Jan 3, 2025 by
tancheng
[P3] Allow parameterizable number of registers serving as the input operands for operation/computation
new feature
New feature or request
#52
opened Dec 29, 2024 by
tancheng
[P1] Allow tile issue New feature or request
TERMINATE
signals on ring (within one CGRA) towards controller
new feature
#48
opened Dec 24, 2024 by
tancheng
[P1] Provide e2e simulation/verification for ring-multi-cgra
new feature
New feature or request
#44
opened Dec 18, 2024 by
tancheng
[P2] Cleanup and update
bug
Something isn't working
new feature
New feature or request
#39
opened Dec 11, 2024 by
tancheng
[P1] Integrate NoC to scale it up/out
new feature
New feature or request
#29
opened Nov 26, 2024 by
tancheng
[P2] Easy way to program CGRA
new feature
New feature or request
#28
opened Nov 26, 2024 by
tancheng
4 tasks
[P1] Predicate should be associated with specific control signal
bug
Something isn't working
new feature
New feature or request
#27
opened Nov 23, 2024 by
tancheng
[P1] Data arrival-dependent execution and cycle-based execution
new feature
New feature or request
#26
opened Nov 23, 2024 by
tancheng
[P2] Simulation traces are not understandable for human being
documentation
Improvements or additions to documentation
new feature
New feature or request
test
#23
opened Nov 18, 2024 by
tancheng
[P0] Synthesis-friendly tile design
bug
Something isn't working
new feature
New feature or request
#13
opened Nov 4, 2023 by
tancheng
[P2] Installation and Data Preloading Issue
new feature
New feature or request
test
#11
opened Aug 31, 2023 by
shourovrm
[P3] Tutorial
documentation
Improvements or additions to documentation
#4
opened Feb 10, 2023 by
tancheng
4 tasks
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