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[feature] Replace en/rdy with val/rdy for ctrl mem and provide test
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,78 @@ | ||
| """ | ||
| ========================================================================== | ||
| RingMultiCtrlMemDynamicRTL.py | ||
| ========================================================================== | ||
| Ring connecting multiple control memories. | ||
| Author : Cheng Tan | ||
| Date : Dec 22, 2024 | ||
| """ | ||
|
|
||
| from pymtl3 import * | ||
| from pymtl3.stdlib.primitive import RegisterFile | ||
| from .CtrlMemDynamicRTL import CtrlMemDynamicRTL | ||
| from ...lib.basic.en_rdy.ifcs import SendIfcRTL | ||
| from ...lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL | ||
| from ...lib.opt_type import * | ||
| from ...noc.PyOCN.pymtl3_net.ringnet.RingNetworkRTL import RingNetworkRTL | ||
| from ...cgra.CGRAWithCrossbarDataMemRTL import CGRAWithCrossbarDataMemRTL | ||
| from ...noc.PyOCN.pymtl3_net.ocnlib.ifcs.positions import mk_ring_pos | ||
|
|
||
| class RingMultiCtrlMemDynamicRTL(Component): | ||
|
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||
| def construct(s, CtrlPktType, CtrlSignalType, width, height, | ||
| ctrl_mem_size, num_fu_inports, num_fu_outports, | ||
| num_tile_inports, num_tile_outports, | ||
| ctrl_count_per_iter = 4, total_ctrl_steps = 4): | ||
|
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||
| # Constant | ||
| num_terminals = width * height | ||
| CtrlRingPos = mk_ring_pos(num_terminals) | ||
| s.num_terminals = width * height | ||
| # CtrlAddrType = mk_bits(clog2(ctrl_mem_size)) | ||
| # ControllerIdType = mk_bits(clog2(num_terminals)) | ||
|
|
||
| # Interface | ||
| # # Request from/to CPU. | ||
| # s.recv_from_cpu = RecvIfcRTL(CGRADataType) | ||
| # s.send_to_cpu = SendIfcRTL(CGRADataType) | ||
| # s.recv_waddr = [[RecvIfcRTL(CtrlAddrType) for _ in range(s.num_tiles)] | ||
| # for _ in range(s.num_terminals)] | ||
| # s.recv_wopt = [[RecvIfcRTL(CtrlType) for _ in range(s.num_tiles)] | ||
| # for _ in range(s.num_terminals)] | ||
| s.send_ctrl = [SendIfcRTL(CtrlSignalType) for _ in range(s.num_terminals)] | ||
| s.recv_pkt_from_controller = ValRdyRecvIfcRTL(CtrlPktType) | ||
|
|
||
| # Components | ||
| # s.cgra = [CGRAWithCrossbarDataMemRTL( | ||
| # CGRADataType, PredicateType, CtrlType, NocPktType, CmdType, | ||
| # ControllerIdType, terminal_id, width, height, ctrl_mem_size, | ||
| # data_mem_size_global, data_mem_size_per_bank, num_banks_per_cgra, | ||
| # num_ctrl, total_steps, FunctionUnit, FuList, controller2addr_map, | ||
| # preload_data = None, preload_const = None) | ||
| # for terminal_id in range(s.num_terminals)] | ||
| s.ctrl_memories = [ | ||
| CtrlMemDynamicRTL(CtrlPktType, CtrlSignalType, ctrl_mem_size, | ||
| num_fu_inports, num_fu_outports, num_tile_inports, | ||
| num_tile_outports, ctrl_count_per_iter, | ||
| total_ctrl_steps) for terminal_id in range(s.num_terminals)] | ||
| s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, num_terminals, 0) | ||
|
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||
| # Connections | ||
| for i in range(s.num_terminals): | ||
| s.ctrl_ring.send[i] //= s.ctrl_memories[i].recv_pkt | ||
|
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||
| s.ctrl_ring.recv[0] //= s.recv_pkt_from_controller | ||
| for i in range(1, s.num_terminals): | ||
| s.ctrl_ring.recv[i].val //= 0 | ||
| s.ctrl_ring.recv[i].msg //= CtrlPktType() | ||
|
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||
| for i in range(s.num_terminals): | ||
| s.ctrl_memories[i].send_ctrl //= s.send_ctrl[i] | ||
|
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||
| def line_trace(s): | ||
| res = "||\n".join([(("[ctrl_memory["+str(i)+"]: ") + x.line_trace()) | ||
| for (i,x) in enumerate(s.ctrl_memories)]) | ||
| res += " ## ctrl_ring: " + s.ctrl_ring.line_trace() | ||
| return res | ||
|
|
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,147 @@ | ||
| """ | ||
| ========================================================================== | ||
| CtrlMemDynamicRTL_test.py | ||
| ========================================================================== | ||
| Test cases for control memory with command-based action handling. | ||
| Author : Cheng Tan | ||
| Date : Dec 21, 2024 | ||
| """ | ||
|
|
||
| from pymtl3 import * | ||
| from ..RingMultiCtrlMemDynamicRTL import RingMultiCtrlMemDynamicRTL | ||
| from ....fu.single.AdderRTL import AdderRTL | ||
| from ....lib.basic.en_rdy.test_sinks import TestSinkRTL | ||
| from ....lib.basic.en_rdy.test_srcs import TestSrcRTL | ||
| from ....lib.basic.val_rdy.SourceRTL import SourceRTL as ValRdyTestSrcRTL | ||
| from ....lib.messages import * | ||
| from ....lib.cmd_type import * | ||
| from ....lib.opt_type import * | ||
|
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||
| #------------------------------------------------------------------------- | ||
| # Test harness | ||
| #------------------------------------------------------------------------- | ||
|
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||
| class TestHarness( Component ): | ||
|
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||
| def construct( s, DUT, DataType, PredicateType, CtrlPktType, | ||
| CtrlSignalType, ctrl_mem_size, width, height, | ||
| data_mem_size, num_fu_inports, num_fu_outports, | ||
| num_tile_inports, num_tile_outports, ctrl_pkts, | ||
| sink_msgs): | ||
|
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| s.width = width | ||
| s.height = height | ||
| s.src_pkt = ValRdyTestSrcRTL(CtrlPktType, ctrl_pkts) | ||
| s.sink_out = [TestSinkRTL(CtrlSignalType, sink_msgs[i]) | ||
| for i in range(width * height)] | ||
|
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| s.dut = \ | ||
| DUT(CtrlPktType, CtrlSignalType, width, height, | ||
| ctrl_mem_size, num_fu_inports, num_fu_outports, | ||
| num_tile_inports, num_tile_outports, | ||
| len(ctrl_pkts), len(ctrl_pkts)) | ||
|
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||
| connect(s.src_pkt.send, s.dut.recv_pkt_from_controller) | ||
| for i in range(width * height): | ||
| connect(s.dut.send_ctrl[i], s.sink_out[i].recv) | ||
|
|
||
| def done(s): | ||
| if not s.src_pkt.done(): | ||
| return False | ||
| for i in range(s.width * s.height): | ||
| if not s.sink_out[i].done(): | ||
| return False | ||
| return True | ||
|
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||
| def line_trace(s): | ||
| return s.dut.line_trace() | ||
|
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||
| def run_sim(test_harness, max_cycles = 40): | ||
| test_harness.elaborate() | ||
| test_harness.apply(DefaultPassGroup()) | ||
| test_harness.sim_reset() | ||
|
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| # Run simulation | ||
|
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||
| ncycles = 0 | ||
| print() | ||
| print("{}:{}".format(ncycles, test_harness.line_trace())) | ||
| while not test_harness.done() and ncycles < max_cycles: | ||
| test_harness.sim_tick() | ||
| ncycles += 1 | ||
| print("{}:{}".format( ncycles, test_harness.line_trace())) | ||
|
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| # Check timeout | ||
|
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||
| assert ncycles < max_cycles | ||
|
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| test_harness.sim_tick() | ||
| test_harness.sim_tick() | ||
| test_harness.sim_tick() | ||
|
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||
| def test_Ctrl(): | ||
| MemUnit = RingMultiCtrlMemDynamicRTL | ||
| DataType = mk_data(16, 1) | ||
| PredicateType = mk_predicate(1, 1) | ||
| ctrl_mem_size = 16 | ||
| ctrl_addr_nbits = clog2(ctrl_mem_size) | ||
| data_mem_size = 8 | ||
| num_fu_inports = 2 | ||
| num_fu_outports = 2 | ||
| num_tile_inports = 4 | ||
| num_tile_outports = 4 | ||
| width = 2 | ||
| height = 2 | ||
| num_terminals = width * height | ||
| num_ctrl_actions = 6 | ||
| ctrl_action_nbits = clog2(num_ctrl_actions) | ||
| num_ctrl_operations = 64 | ||
| CtrlPktType = mk_ring_across_tiles_pkt(num_terminals, | ||
| num_ctrl_actions, | ||
| ctrl_mem_size, | ||
| num_ctrl_operations, | ||
| num_fu_inports, | ||
| num_fu_outports, | ||
| num_tile_inports, | ||
| num_tile_outports) | ||
| CtrlSignalType = mk_separate_ctrl(num_ctrl_operations, | ||
| num_fu_inports, | ||
| num_fu_outports, | ||
| num_tile_inports, | ||
| num_tile_outports) | ||
| FuInType = mk_bits(clog2(num_fu_inports + 1)) | ||
| pickRegister = [FuInType(x + 1) for x in range(num_fu_inports)] | ||
|
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||
| src_ctrl_pkt = [ # src dst vc_id opq cmd_type addr operation predicate | ||
| CtrlPktType(0, 0, 0, 0, CMD_CONFIG, 0, OPT_ADD, b1(0), pickRegister), | ||
| CtrlPktType(0, 1, 0, 0, CMD_CONFIG, 1, OPT_SUB, b1(0), pickRegister), | ||
| CtrlPktType(0, 2, 0, 0, CMD_CONFIG, 0, OPT_SUB, b1(0), pickRegister), | ||
| CtrlPktType(0, 3, 0, 0, CMD_CONFIG, 1, OPT_ADD, b1(0), pickRegister), | ||
| CtrlPktType(0, 3, 0, 0, CMD_CONFIG, 0, OPT_SUB, b1(0), pickRegister), | ||
| CtrlPktType(0, 0, 0, 0, CMD_CONFIG, 1, OPT_SUB, b1(0), pickRegister), | ||
| CtrlPktType(0, 0, 0, 0, CMD_LAUNCH, 0, OPT_SUB, b1(0), pickRegister), | ||
| CtrlPktType(0, 1, 0, 0, CMD_CONFIG, 0, OPT_ADD, b1(0), pickRegister), | ||
| CtrlPktType(0, 1, 0, 0, CMD_LAUNCH, 0, OPT_SUB, b1(0), pickRegister), | ||
| CtrlPktType(0, 2, 0, 0, CMD_CONFIG, 1, OPT_ADD, b1(0), pickRegister), | ||
| CtrlPktType(0, 2, 0, 0, CMD_LAUNCH, 0, OPT_ADD, b1(0), pickRegister), | ||
| CtrlPktType(0, 3, 0, 0, CMD_LAUNCH, 0, OPT_ADD, b1(0), pickRegister)] | ||
|
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||
| sink_out = [ | ||
| [CtrlSignalType(OPT_ADD, 0, pickRegister), | ||
| CtrlSignalType(OPT_SUB, 0, pickRegister)], | ||
| # Ctrl memory 1 first write into address 1, then address 0. | ||
| [CtrlSignalType(OPT_ADD, 0, pickRegister), | ||
| CtrlSignalType(OPT_SUB, 0, pickRegister)], | ||
|
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| [CtrlSignalType(OPT_SUB, 0, pickRegister), | ||
| CtrlSignalType(OPT_ADD, 0, pickRegister)], | ||
|
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| [CtrlSignalType(OPT_SUB, 0, pickRegister), | ||
| CtrlSignalType(OPT_ADD, 0, pickRegister)]] | ||
| th = TestHarness(MemUnit, DataType, PredicateType, CtrlPktType, CtrlSignalType, | ||
| ctrl_mem_size, width, height, data_mem_size, num_fu_inports, | ||
| num_fu_outports, num_tile_inports, num_tile_outports, | ||
| src_ctrl_pkt, sink_out) | ||
| run_sim(th) | ||
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