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Merge pull request #47 from tancheng/deliver-inst-via-ring
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Deliver ctrl signal via ring
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@tancheng
tancheng authored Dec 24, 2024
2 parents d1dd6b3 + d2f625b commit 49a4018
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Showing 25 changed files with 1,279 additions and 926 deletions.
15 changes: 7 additions & 8 deletions .github/workflows/python-package.yml
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Expand Up @@ -65,20 +65,19 @@ jobs:
# Kingmesh topology CGRA translation.
pytest ../cgra/translate/VectorCGRAKingMeshRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
# Separate crossbars CGRA simulation/translation.
pytest ../cgra/test/CGRASeparateCrossbarRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
pytest ../cgra/translate/CGRASeparateCrossbarRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
pytest ../cgra/translate/CgraCrossbarDataMemRingCtrlMemRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
# 3x2 CGRA performs 2x2 matmul translation.
pytest ../cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
pytest ../systolic/translate/CgraMemBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
# 3x3 CGRA performs 2x2 matmul simulation/translation.
pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short
pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
pytest ../systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short
pytest ../systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
# Ring network simulation.
pytest ../noc/PyOCN/pymtl3_net/ringnet/test/RingNetworkRTL_test.py --tb=short -sv
# CGRA with separate crossbars (for tiles and FUs), crossbar-based data
# memory (for multi-bank), and controller.
pytest --tb=short -sv ../cgra/translate/CGRAWithCrossbarDataMemRTL_test.py --test-verilog --dump-vtb --dump-vcd
# memory (for multi-bank), ring-based control memories, and controller.
pytest --tb=short -sv ../cgra/translate/CgraCrossbarDataMemRingCtrlMemRTL_test.py --test-verilog --dump-vtb --dump-vcd
# CGRAs are interconnected with ring topology. The CGRA contains
# separate crossbars (for tiles and FUs), crossbar-based data memory (for
# multi-bank), and controller.
pytest --tb=short -sv ../scale_out/translate/RingMultiCGRARTL_test.py --test-verilog --dump-vtb --dump-vcd
pytest --tb=short -sv ../scale_out/translate/RingMultiCgraRingCtrlMemRTL_test.py --test-verilog --dump-vtb --dump-vcd
104 changes: 0 additions & 104 deletions cgra/CGRASeparateCrossbarRTL.py
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113 changes: 77 additions & 36 deletions cgra/CGRAWithCrossbarDataMemRTL.py → cgra/CgraCrossbarDataMemRingCtrlMemRTL.py
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@@ -1,13 +1,14 @@
"""
=========================================================================
CGRAWithCrossbarDataMemRTL.py
CgraCrossbarDataMemRingCtrlMemRTL.py
=========================================================================
Author : Cheng Tan
Date : Dec 13, 2024
Date : Dec 22, 2024
"""

from pymtl3 import *
from ..controller.ControllerRTL import ControllerRTL
from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL
from ..fu.single.MemUnitRTL import MemUnitRTL
from ..fu.single.AdderRTL import AdderRTL
Expand All @@ -19,59 +20,71 @@
from ..mem.data.DataMemWithCrossbarRTL import DataMemWithCrossbarRTL
from ..noc.ChannelNormalRTL import ChannelNormalRTL
from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL
from ..noc.PyOCN.pymtl3_net.ocnlib.ifcs.positions import mk_ring_pos
from ..noc.PyOCN.pymtl3_net.ringnet.RingNetworkRTL import RingNetworkRTL
from ..tile.TileSeparateCrossbarRTL import TileSeparateCrossbarRTL
from ..controller.ControllerRTL import ControllerRTL


class CGRAWithCrossbarDataMemRTL(Component):

def construct(s, DataType, PredicateType, CtrlType, NocPktType,
CmdType, ControllerIdType, controller_id,
class CgraCrossbarDataMemRingCtrlMemRTL(Component):
def construct(s, DataType, PredicateType, CtrlPktType, CtrlSignalType,
NocPktType, CmdType, ControllerIdType, controller_id,
width, height, ctrl_mem_size, data_mem_size_global,
data_mem_size_per_bank, num_banks_per_cgra, num_ctrl,
total_steps, FunctionUnit, FuList, controller2addr_map,
preload_data = None, preload_const = None):

s.num_tiles = width * height
CtrlRingPos = mk_ring_pos(s.num_tiles)
s.num_mesh_ports = 4
CtrlAddrType = mk_bits(clog2(ctrl_mem_size))
DataAddrType = mk_bits(clog2(data_mem_size_global))
assert(data_mem_size_per_bank * num_banks_per_cgra <= \
data_mem_size_global)

# Interfaces
s.recv_waddr = [RecvIfcRTL(CtrlAddrType) for _ in range(s.num_tiles)]
s.recv_wopt = [RecvIfcRTL(CtrlType) for _ in range(s.num_tiles)]
# s.recv_waddr = [RecvIfcRTL(CtrlAddrType) for _ in range(s.num_tiles)]
# s.recv_wopt = [RecvIfcRTL(CtrlSignalType) for _ in range(s.num_tiles)]
s.recv_from_cpu_ctrl_pkt = ValRdyRecvIfcRTL(CtrlPktType)

# Explicitly provides the ValRdyRecvIfcRTL in the library, as the
# translation pass sometimes not able to distinguish the
# EnRdyRecvIfcRTL from it.
s.recv_from_noc = ValRdyRecvIfcRTL(NocPktType)
s.send_to_noc = ValRdySendIfcRTL(NocPktType)

# Interfaces on the boundary of the CGRA.
s.recv_data_on_boundary_south = [RecvIfcRTL(DataType) for _ in range(width)]
s.send_data_on_boundary_south = [SendIfcRTL(DataType) for _ in range(width)]
s.recv_data_on_boundary_north = [RecvIfcRTL(DataType) for _ in range(width)]
s.send_data_on_boundary_north = [SendIfcRTL(DataType) for _ in range(width)]

s.recv_data_on_boundary_east = [RecvIfcRTL(DataType) for _ in range(height)]
s.send_data_on_boundary_east = [SendIfcRTL(DataType) for _ in range(height)]
s.recv_data_on_boundary_west = [RecvIfcRTL(DataType) for _ in range(height)]
s.send_data_on_boundary_west = [SendIfcRTL(DataType) for _ in range(height)]

# s.recv_towards_controller = RecvIfcRTL(DataType)
# s.send_from_controller = SendIfcRTL(DataType)


# Components
if preload_const == None:
preload_const = [[DataType(0, 0)] for _ in range(width*height)]
s.tile = [TileSeparateCrossbarRTL(DataType, PredicateType, CtrlType,
ctrl_mem_size, data_mem_size_global,
num_ctrl, total_steps, 4, 2, s.num_mesh_ports,
s.num_mesh_ports, const_list = preload_const[i])
for i in range( s.num_tiles)]
s.tile = [TileSeparateCrossbarRTL(
DataType, PredicateType, CtrlPktType, CtrlSignalType, ctrl_mem_size,
data_mem_size_global, num_ctrl, total_steps, 4, 2,
s.num_mesh_ports, s.num_mesh_ports,
const_list = preload_const[i]) for i in range( s.num_tiles)]
s.data_mem = DataMemWithCrossbarRTL(NocPktType, DataType,
data_mem_size_global,
data_mem_size_per_bank,
num_banks_per_cgra, height, height,
num_banks_per_cgra,
height, height,
preload_data)
s.controller = ControllerRTL(ControllerIdType, CmdType, NocPktType,
DataType, DataAddrType, controller_id,
controller2addr_map)
s.controller = ControllerRTL(ControllerIdType, CmdType, CtrlPktType,
NocPktType, DataType, DataAddrType,
controller_id, controller2addr_map)
s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 0)

# Connections

# Connects data memory with controller.
# s.data_mem.recv_from_noc //= s.controller.send_to_master
# s.data_mem.send_to_noc //= s.controller.recv_from_master
Expand All @@ -90,12 +103,24 @@ def construct(s, DataType, PredicateType, CtrlType, NocPktType,
s.recv_from_noc //= s.controller.recv_from_noc
s.send_to_noc //= s.controller.send_to_noc

# Connects the ctrl interface between CPU and controller.
s.recv_from_cpu_ctrl_pkt //= s.controller.recv_from_cpu_ctrl_pkt

# s.recv_towards_controller //= s.controller.recv_from_master
# s.send_from_controller //= s.controller.send_to_master

# Connects ring with each control memory.
for i in range(s.num_tiles):
s.recv_waddr[i] //= s.tile[i].recv_waddr
s.recv_wopt[i] //= s.tile[i].recv_wopt
s.ctrl_ring.send[i] //= s.tile[i].recv_ctrl_pkt

s.ctrl_ring.recv[0] //= s.controller.send_to_ctrl_ring_ctrl_pkt
for i in range(1, s.num_tiles):
s.ctrl_ring.recv[i].val //= 0
s.ctrl_ring.recv[i].msg //= CtrlPktType()

for i in range(s.num_tiles):
# s.recv_waddr[i] //= s.tile[i].recv_waddr
# s.recv_wopt[i] //= s.tile[i].recv_wopt

if i // width > 0:
s.tile[i].send_data[PORT_SOUTH] //= s.tile[i-width].recv_data[PORT_NORTH]
Expand All @@ -110,24 +135,40 @@ def construct(s, DataType, PredicateType, CtrlType, NocPktType,
s.tile[i].send_data[PORT_EAST] //= s.tile[i+1].recv_data[PORT_WEST]

if i // width == 0:
s.tile[i].send_data[PORT_SOUTH].rdy //= 0
s.tile[i].recv_data[PORT_SOUTH].en //= 0
s.tile[i].recv_data[PORT_SOUTH].msg //= DataType(0, 0)
s.tile[i].send_data[PORT_SOUTH] //= s.send_data_on_boundary_south[i % width]
s.tile[i].recv_data[PORT_SOUTH] //= s.recv_data_on_boundary_south[i % width]

if i // width == height - 1:
s.tile[i].send_data[PORT_NORTH].rdy //= 0
s.tile[i].recv_data[PORT_NORTH].en //= 0
s.tile[i].recv_data[PORT_NORTH].msg //= DataType(0, 0)
s.tile[i].send_data[PORT_NORTH] //= s.send_data_on_boundary_north[i % width]
s.tile[i].recv_data[PORT_NORTH] //= s.recv_data_on_boundary_north[i % width]

if i % width == 0:
s.tile[i].send_data[PORT_WEST].rdy //= 0
s.tile[i].recv_data[PORT_WEST].en //= 0
s.tile[i].recv_data[PORT_WEST].msg //= DataType(0, 0)
s.tile[i].send_data[PORT_WEST] //= s.send_data_on_boundary_west[i // width]
s.tile[i].recv_data[PORT_WEST] //= s.recv_data_on_boundary_west[i // width]

if i % width == width - 1:
s.tile[i].send_data[PORT_EAST].rdy //= 0
s.tile[i].recv_data[PORT_EAST].en //= 0
s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0)
s.tile[i].send_data[PORT_EAST] //= s.send_data_on_boundary_east[i // width]
s.tile[i].recv_data[PORT_EAST] //= s.recv_data_on_boundary_east[i // width]

# if i // width == 0:
# s.tile[i].send_data[PORT_SOUTH].rdy //= 0
# s.tile[i].recv_data[PORT_SOUTH].en //= 0
# s.tile[i].recv_data[PORT_SOUTH].msg //= DataType(0, 0)

# if i // width == height - 1:
# s.tile[i].send_data[PORT_NORTH].rdy //= 0
# s.tile[i].recv_data[PORT_NORTH].en //= 0
# s.tile[i].recv_data[PORT_NORTH].msg //= DataType(0, 0)

# if i % width == 0:
# s.tile[i].send_data[PORT_WEST].rdy //= 0
# s.tile[i].recv_data[PORT_WEST].en //= 0
# s.tile[i].recv_data[PORT_WEST].msg //= DataType(0, 0)

# if i % width == width - 1:
# s.tile[i].send_data[PORT_EAST].rdy //= 0
# s.tile[i].recv_data[PORT_EAST].en //= 0
# s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0)

if i % width == 0:
s.tile[i].to_mem_raddr //= s.data_mem.recv_raddr[i//width]
Expand All @@ -141,7 +182,6 @@ def construct(s, DataType, PredicateType, CtrlType, NocPktType,
s.tile[i].to_mem_waddr.rdy //= 0
s.tile[i].to_mem_wdata.rdy //= 0


# Line trace
def line_trace( s ):
# str = "||".join([ x.element.line_trace() for x in s.tile ])
Expand All @@ -150,3 +190,4 @@ def line_trace( s ):
for (i,x) in enumerate(s.tile) ])
res += "\n :: [" + s.data_mem.line_trace() + "] \n"
return res

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