[test] systolic array simulation

tancheng · Jan 10, 2025 · f5193e7 · f5193e7
1 parent 3803cb7
commit f5193e7
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Showing 3 changed files with 13 additions and 9 deletions.
diff --git a/lib/messages.py b/lib/messages.py
@@ -303,7 +303,7 @@ def mk_multi_cgra_noc_pkt(ncols = 2, nrows = 2, opaque_nbits = 8, vc = 2,
                           data_nbits = 16, predicate_nbits = 1,
                           prefix="MeshMultiCGRAPacket"):
 
-  IdType = mk_bits(clog2(ncols * nrows))
+  IdType = mk_bits(max(clog2(ncols * nrows), 1))
   XType = mk_bits(max(clog2(ncols), 1))
   YType = mk_bits(max(clog2(nrows), 1))
   OpqType = mk_bits(opaque_nbits)

diff --git a/systolic/CgraSystolicArrayRTL.py b/systolic/CgraSystolicArrayRTL.py
@@ -77,10 +77,13 @@ def construct(s, DataType, PredicateType, CtrlPktType, CtrlSignalType,
                                         # 4 read/write from tiles and 1 read/write from NoC.
                                         4, 4,
                                         preload_data)
+    idTo2d_map = {0: [0, 0]}
     s.controller = ControllerRTL(ControllerIdType, CmdType, CtrlPktType,
                                  NocPktType, DataType, DataAddrType,
-                                 controller_id, controller2addr_map)
-    s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 0)
+                                 1, 1,
+                                 controller_id, controller2addr_map,
+                                 idTo2d_map)
+    s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 1)
 
     # Connections
     # Connects data memory with controller.

diff --git a/systolic/test/Cgra3x3MemRightAndBottomRTL_matmul_2x2_test.py b/systolic/test/Cgra3x3MemRightAndBottomRTL_matmul_2x2_test.py
@@ -151,7 +151,7 @@ def test_CGRA_systolic(cmdline_opts):
   num_banks_per_cgra = 4
   width = 3
   height = 3
-  num_terminals = 2
+  num_terminals = 1
   num_ctrl_actions = 6
   num_ctrl_operations = 64
   TileInType = mk_bits(clog2(num_tile_inports + 1))
@@ -168,7 +168,7 @@ def test_CGRA_systolic(cmdline_opts):
   FuList = [SeqMulAdderRTL, AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL]
 
   CmdType = mk_bits(4)
-  ControllerIdType = mk_bits(clog2(num_terminals))
+  ControllerIdType = mk_bits(max(clog2(num_terminals), 1))
   controller_id = 0
   controller2addr_map = {
           0: [0,  15],
@@ -191,10 +191,11 @@ def test_CGRA_systolic(cmdline_opts):
                        num_tile_inports,
                        num_tile_outports)
 
-  NocPktType = mk_ring_multi_cgra_pkt(nrouters = num_terminals,
-                                      addr_nbits = addr_nbits,
-                                      data_nbits = 32,
-                                      predicate_nbits = 1)
+  NocPktType = mk_multi_cgra_noc_pkt(ncols = 1,
+                                     nrows = 1,
+                                     addr_nbits = addr_nbits,
+                                     data_nbits = 32,
+                                     predicate_nbits = 1)
   pick_register = [FuInType(x + 1) for x in range(num_fu_inports)]
 
   src_opt_per_tile = [