23 simulation traces are not understandable for human being #43

yuqisun · 2024-12-16T09:25:56Z

Attched log sample of VectorCGRAKingMeshRTL_test, please help review, thanks. (There may some trace logs be missed, too many, will update during developing, WDYT)

VectorCGRAKingMeshRTL_test_log.txt

Also sync changes from master.

…rstandable-for-human-being

…icate_in list instead of 0x

…erstandable-for-human-being' into 23-simulation-traces-are-not-understandable-for-human-being

tancheng · 2024-12-20T02:49:23Z

Hi @yuqisun, thanks for the PR,

+--------------+----------------+---------+------+-----+
|port_direction|     payload    |predicate|bypass|delay|
+--------------+----------------+---------+------+-----+
|     NORTH    |0000000000000000|    0    |   0  |  0  |
+--------------+----------------+---------+------+-----+

Can we distinguish the port_direction into inport_direction and outport_direction?

outport: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
predicate_in: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]

Can we have the meaningful content inside those array? Say, outport: [N, S, -, -, ..., -]?

===>
- channel_recv:

+----------------+---------+------+-----+
|     payload    |predicate|bypass|delay|
+----------------+---------+------+-----+
|0000000000000000|    0    |   0  |  0  |
+----------------+---------+------+-----+
|0000000000000000|    0    |   0  |  0  |
+----------------+---------+------+-----+

What is above channel_recv, is this necessary to be shown? If yes, can we provide its name?

yuqisun · 2024-12-20T15:10:18Z

Hi,

channel_recv is from:
[ x.recv.msg.__dict__ for x in s.channel ] <=== s.channel = [ ChannelRTL( DataType ) for _ in range( num_xbar_outports ) ] <=== num_xbar_outports = num_fu_inports + num_connect_outports.

So channel should be the lines of crossbar, channel_recv should be the inports which in green in below picture, am I correct?

And there's also channel_send: [ x.send.msg.__dict__ for x in s.channel ] which should be the outports in blue in picture?

tancheng · 2024-12-20T22:00:02Z

Hi,

channel_recv is from: [ x.recv.msg.__dict__ for x in s.channel ] <=== s.channel = [ ChannelRTL( DataType ) for _ in range( num_xbar_outports ) ] <=== num_xbar_outports = num_fu_inports + num_connect_outports.

So channel should be the lines of crossbar, channel_recv should be the inports which in green in below picture, am I correct?

And there's also channel_send: [ x.send.msg.__dict__ for x in s.channel ] which should be the outports in blue in picture?

Nope. Channel actually includes registers. The channel.recv is the blue one, the channel.send is the one after the yellow register. Imagine the channel as a pipe, it doesn't contain the xbar, it connects to the xbar.

yuqisun · 2024-12-25T15:54:08Z

How to use `line_trace` and `verbose_trace` in `*_test.py`

There're 2 kinds of formats of trace log:

line_trace: refers to a single-line trace
verbose_trace: prints more details, such as ctrl_mem ...

For example:
cgra/translate/VectorCGRAKingMeshRTL_test.py

def line_trace( s ):
    # verbose trace (test without verilog), uncomment below to use verbose_trace
    # verbosity = 1
    # return s.dut.verbose_trace(verbosity = verbosity)
    return s.dut.line_trace()

Note: --test-verilog mode requires line_trace always as it uses line_trace in python file which is generated by PyMTL instead of defined in VectorCGRA.

tancheng

Plz sync to TOT
Plz enable the verbosity for https://github.com/tancheng/VectorCGRA/blob/master/scale_out/RingMultiCgraRingCtrlMemRTL.py & https://github.com/tancheng/VectorCGRA/blob/master/systolic/CgraMemRightAndBottomRTL.py

Thanks!

.github/workflows/python-package.yml

cgra/CGRAKingMeshRTL.py

…e-for-human-being

cgra/CGRAKingMeshRTL.py

mem/ctrl/CtrlMemRTL.py

tile/TileRTL.py

tile/TileRTL_constant.py

tile/TileSeparateCrossbarRTL.py

cgra/CGRAKingMeshRTL.py

…ordering.

…master/scale_out/RingMultiCgraRingCtrlMemRTL.py & https://github.com/tancheng/VectorCGRA/blob/master/systolic/CgraMemRightAndBottomRTL.py

yuqisun · 2024-12-26T16:07:40Z

Plz sync to TOT

Plz enable the verbosity for https://github.com/tancheng/VectorCGRA/blob/master/scale_out/RingMultiCgraRingCtrlMemRTL.py & https://github.com/tancheng/VectorCGRA/blob/master/systolic/CgraMemRightAndBottomRTL.py

Thanks!

CgraMemRightAndBottomRTL good.
RingMultiCgraRingCtrlMemRTL pending on CtrlMemDynamicRTL and DataMemWithCrossbarRTL, will add tmr.

lib/util/common.py

mem/ctrl/CtrlMemRTL.py

tile/TileRTL.py

2. recv_ctrl_msg_list = [ recv_ctrl_sub_header, recv_ctrl_msg_dict ] -> recv_ctrl_msg_list = [recv_ctrl_sub_header, recv_ctrl_msg_dict] 3. put line_trace() before verbose()

mem/data/DataMemRTL.py

tancheng · 2024-12-27T16:25:55Z

systolic/CgraMemRightAndBottomRTL.py

    # str = "||".join([ x.element.line_trace() for x in s.tile ])
    # str += " :: [" + s.data_mem.line_trace() + "]"
    res = "||\n".join([(("[tile" + str(i) + "]: ") + x.line_trace() + x.ctrl_mem.line_trace())
                       for (i,x) in enumerate(s.tile)])
    res += "\n :: SouthMem [" + s.data_mem_south.line_trace() + "]    \n"
    res += "\n :: EastMem [" + s.data_mem_east.line_trace() + "]    \n"
    return res
+
+
+  def verbose_trace( s, verbosity = 1 ):


Remove the unnecessary space, (keep the one before and after =).

systolic/CgraMemRightAndBottomRTL.py

tancheng · 2024-12-27T16:26:37Z

scale_out/test/RingMultiCgraRingCtrlMemRTL_test.py

@@ -81,6 +81,7 @@ def done(s):
    # return True

  def line_trace(s):
+    # return s.dut.verbose_trace(verbosity = 2)


If this is the way to invoke the verbose_trace(), let's enable it by default for this test?

verbose_trace works for -xvs --tb=short but not --test-verilog, it looks up line_trace(), can test this with -xvs --tb=short for RingMultiCgraRingCtrlMemRTL_test.py, current is pytest --tb=short -sv ../scale_out/translate/RingMultiCgraRingCtrlMemRTL_test.py --test-verilog --dump-vtb --dump-vcd?

Then the xxx_test.py within translate/ folder can have line_trace(), while the one in test/ can have vervose_trace() enabled by default.

Or I guess actually you can control it based on the flag?

def line_trace(s, verbosity=0): if verbosity = 0: return s.dut.line_trace(verbosity) if verbosity = 1: return s.dut.verbose_trace(verbosity) ...... dut = Top() if flags not contains --test-verilog: dut.set_param('top.x.y.z.line_trace', verbosity=1) # Or use a global variable?

Oops, you both are right, controlling by set_param is better, I should use it from the beginning.

Added a line in *_test.py th.set_param('top.dut.line_trace', verbosity = 1), will enable verbose_trace by default and when there's --test-verilog, will ignore verbose itself.

tile/test/TileSeparateCrossbarRTL_test.py

tancheng · 2024-12-27T16:27:29Z

systolic/translate/CgraMemRightAndBottomRTL_matmul_2x2_test.py

@@ -80,6 +80,7 @@ def check_parity(s):
    return True

  def line_trace(s):
+    # return s.dut.verbose_trace(verbosity = 2)


Enable by default?

There're both -xvs --tb=short and --tb=short --test-verilog --dump-vtb --dump-vcd in testcases, if enable verbose_trace by default, can I remove and ignore --tb=short --test-verilog --dump-vtb --dump-vcd case in action workflow?

Make it by set_param.

tancheng · 2024-12-28T02:15:36Z

Hi @yuqisun, I am currently working on a huge cleanup. Plz let me merge first... So then you can sync and merge. Sorry about the inconvenience.

You can move to #44, thanks~!

yuqisun and others added 24 commits December 9, 2024 22:58

Simulation traces are not understandable for human being tancheng#23

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Merge branch 'tancheng:master' into 23-simulation-traces-are-not-unde…

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…rstandable-for-human-being

Simulation traces are not understandable for human being tancheng#23

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Simulation traces are not understandable for human being tancheng#23

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Simulation traces are not understandable for human being tancheng#23

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Populate values for #ctrl and use decimal for fu_in, outport and pred…

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…icate_in list instead of 0x

Populate values for #ctrl and use decimal for fu_in, outport and pred…

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…icate_in list instead of 0x

Populate values for #ctrl and use decimal for fu_in, outport and pred…

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…icate_in list instead of 0x

Use decimal for trace bit values instead of 0x

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Format Ctrl and Crossbar RTL

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Format Ctrl and Crossbar RTL

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Format data mem

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Simulation traces are not understandable for human being tancheng#23

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Simulation traces are not understandable for human being tancheng#23

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Simulation traces are not understandable for human being tancheng#23

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Simulation traces are not understandable for human being tancheng#23

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Populate values for #ctrl and use decimal for fu_in, outport and pred…

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…icate_in list instead of 0x

Populate values for #ctrl and use decimal for fu_in, outport and pred…

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…icate_in list instead of 0x

Populate values for #ctrl and use decimal for fu_in, outport and pred…

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…icate_in list instead of 0x

Use decimal for trace bit values instead of 0x

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Format Ctrl and Crossbar RTL

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Format Ctrl and Crossbar RTL

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Format data mem

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Merge remote-tracking branch 'origin/23-simulation-traces-are-not-und…

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…erstandable-for-human-being' into 23-simulation-traces-are-not-understandable-for-human-being

yuqisun requested a review from tancheng December 19, 2024 14:47

yuqisun added 2 commits December 21, 2024 19:24

format FlexibleFuRTL

ede9365

format with directions and addr

7d04f0c

tancheng reviewed Dec 25, 2024

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[P2] Simulation traces are not understandable for human being #23

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yuqisun force-pushed the 23-simulation-traces-are-not-understandable-for-human-being branch from 79d15c1 to 9ed1abb Compare December 26, 2024 01:51

yuqisun added 7 commits December 26, 2024 15:55

verbose_trace calls verbose_trace, leave line_trace as it is.

e9054d8

Move to after from pymtl3 import *, we are sorting these in alphabet …

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…ordering.

Optimize imports order and move common dicts to common

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Test with verilog.

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extract common logic for verbose_trace

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extract common logic for verbose_trace

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enable the verbosity for https://github.com/tancheng/VectorCGRA/blob/…

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…master/scale_out/RingMultiCgraRingCtrlMemRTL.py & https://github.com/tancheng/VectorCGRA/blob/master/systolic/CgraMemRightAndBottomRTL.py

tancheng reviewed Dec 26, 2024

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yuqisun added 3 commits December 27, 2024 16:08

1. TILE_PORT_DIRECTION_DICT -> TILE_PORT_DIRECTION_DICT_DESC

57dfc34

2. recv_ctrl_msg_list = [ recv_ctrl_sub_header, recv_ctrl_msg_dict ] -> recv_ctrl_msg_list = [recv_ctrl_sub_header, recv_ctrl_msg_dict] 3. put line_trace() before verbose()

put line_trace() before verbose()

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Add verbose trace for CtrlMemDynamicRTL.py

8f9ecd8

tancheng approved these changes Dec 27, 2024

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yuqisun added 5 commits December 28, 2024 20:45

Remove the unnecessary space.

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Remove the unnecessary space.

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Remove the unnecessary space.

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enable verbose_trace by default

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Control verbose_trace by set_param.

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23 simulation traces are not understandable for human being #43

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23 simulation traces are not understandable for human being #43

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How to use line_trace and verbose_trace in *_test.py

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How to use `line_trace` and `verbose_trace` in `*_test.py`