update data preloading

[yyan7223]

[tancheng]

Ring is the NoC for multiple CGRAs? Or for multiple tiles?

[yyan7223]

I mean the multiple banks in the SPM of one CGRA.

[tancheng]

Then all the banks are connected to one controller:

VectorCGRA/cgra/CgraRTL.py

Lines 89 to 91 in 4688d88

	s.data_mem.recv_raddr[height] //= s.controller.send_to_tile_load_request_addr
	s.data_mem.recv_waddr[height] //= s.controller.send_to_tile_store_request_addr
	s.data_mem.recv_wdata[height] //= s.controller.send_to_tile_store_request_data

Why do we need to send pkt/msg on ring for SRAM banks?

[tancheng]

Ah, do you mean the SRAM banks on other CGRAs?

[yyan7223]

No, just local SRAM banks for current CGRA.
This is for preloading data to SRAM banks before executing, just like we load ctrl signals to tiles

[tancheng]

Would it be better if this message just have data and addr? The cgra id and bank id could be inferred based on the addr2controller_lut, and send through

VectorCGRA/controller/ControllerRTL.py

Lines 52 to 53 in 4688d88

	s.send_to_tile_store_request_addr_queue = ChannelRTL(CGRAAddrType, latency = 1)
	s.send_to_tile_store_request_data_queue = ChannelRTL(CGRADataType, latency = 1)

, which are already connected to the write ports of the data memory.

[tancheng]

I draw the arch figure for you:

[tancheng]

Why do we remove _cpu_ here? It can come from other places?

[yyan7223]

If we have 100 cgras, I don't think let CPU connect all of them is a good idea.
Instead, only the first cgra connect to cpu, and the rest of cgras are connected sequentially, which will be more synthesised&P&R friendly I believe?
Or I change it back.

[tancheng]

Yes, we are aligned on this, CPU only talks to the first controller. Thus, we already have:

• pkg from NoC:

  VectorCGRA/controller/ControllerRTL.py

  Line 29 in 4688d88

  s.recv_from_noc = RecvIfcRTL(NocPktType)

• Handler (TODO) upon receiving the pkg from NoC:

  VectorCGRA/controller/ControllerRTL.py

  Line 215 in 4688d88

  # # TODO: Handle other cmd types.

[yyan7223]

I don't understand, then what is the purpose of recv_from_cpu_ctrl_pkt?

[yyan7223]

Don't worry, let me read CgraTemplateRTL.py and understand your design.

[tancheng]

Thanks. And to briefly clarify, recv_from_cpu_ctrl_pkt of the first CGRA/controller would get pkt from CPU then send into the queue recv_ctrl_pkt_queue, then the pkt in the queue would be popped to the inter-CGRA NoC (now is a ring), note that even the CGRA_0's pkt would be sent into the ring and popped, to be uniformed/simplified.

[tancheng]

Why do we remove most of the ifcs? How to handle different types if they are removed.

[yyan7223]

Why do we remove most of the ifcs? How to handle different types if they are removed.

I don't remove them, the green are the updated stuff based on the original

[tancheng]

Why do we remove most of the ifcs? How to handle different types if they are removed.

I don't remove them, the green are the updated stuff based on the original

You mean "added"?