Simulation traces are not understandable for human being #23

[yuqisun]

Better?

5: [tile0]: class: TileRTL, recv: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}] => [recv_opt_msg: {'ctrl': Bits6(0x03), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x1), Bits3(0x2), Bits3(0x3), Bits3(0x4)], 'outport': [Bits4(0x4), Bits4(0x3), Bits4(0x2), Bits4(0x1), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x5), Bits4(0x5), Bits4(0x5), Bits4(0x5)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}] (class: FlexibleFuRTL, [recv: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}]] opt: # (P0) (const: {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, en: 0) ] = [out: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}]] (recv_opt.rdy: 0, recv_in[0].rdy: 0, recv_in[1].rdy: 0, recv_predicate.msg: {'payload': Bits1(0x0), 'predicate': Bits1(0x0)}, (++), recv_opt.en: 0, send[0].en: 0) ) => channel_recv: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}] => channel_send: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}] => out: [{send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}, {send_msg_payload: 0000000000000000, send_msg_predicate: 0}]class: CtrlMemRTL, recv_ctrl_msg: {'ctrl': Bits6(0x02), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x1), Bits3(0x2), Bits3(0x3), Bits3(0x4)], 'outport': [Bits4(0x4), Bits4(0x3), Bits4(0x2), Bits4(0x1), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x5), Bits4(0x5), Bits4(0x5), Bits4(0x5)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]} : out: [{'ctrl': Bits6(0x03), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x1), Bits3(0x2), Bits3(0x3), Bits3(0x4)], 'outport': [Bits4(0x4), Bits4(0x3), Bits4(0x2), Bits4(0x1), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x5), Bits4(0x5), Bits4(0x5), Bits4(0x5)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}, {'ctrl': Bits6(0x03), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x1), Bits3(0x2), Bits3(0x3), Bits3(0x4)], 'outport': [Bits4(0x4), Bits4(0x3), Bits4(0x2), Bits4(0x1), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x5), Bits4(0x5), Bits4(0x5), Bits4(0x5)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}, {'ctrl': Bits6(0x00), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x0), Bits3(0x0), Bits3(0x0), Bits3(0x0)], 'outport': [Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}, {'ctrl': Bits6(0x00), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x0), Bits3(0x0), Bits3(0x0), Bits3(0x0)], 'outport': [Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}, {'ctrl': Bits6(0x00), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x0), Bits3(0x0), Bits3(0x0), Bits3(0x0)], 'outport': [Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}, {'ctrl': Bits6(0x00), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x0), Bits3(0x0), Bits3(0x0), Bits3(0x0)], 'outport': [Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}] : send_ctrl_msg: {'ctrl': Bits6(0x03), 'predicate': Bits1(0x0), 'fu_in': [Bits3(0x1), Bits3(0x2), Bits3(0x3), Bits3(0x4)], 'outport': [Bits4(0x4), Bits4(0x3), Bits4(0x2), Bits4(0x1), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x0), Bits4(0x5), Bits4(0x5), Bits4(0x5), Bits4(0x5)], 'predicate_in': [Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0), Bits1(0x0)]}||

...
data_mem:: [class: DataMemRTL, recv_read_addr: [0, 0, 0, 0] || recv_write_addr: [0, 0, 0, 0] || recv_write_data: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}] || [content: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}]] || send_read_data: [0000000000000000.0.0.0, 0000000000000000.0.0.0, 0000000000000000.0.0.0, 0000000000000000.0.0.0]]

[tancheng]

• Can we format the trace to make it easy to see the port/address/index difference, say,

[tile0]: class: TileRTL, recv: [{'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)}, {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},

to

[tile0]: class: TileRTL, recv: [
  {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},
  {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},

• And maybe even add the index at the beginning of each item:

[tile0]: class: TileRTL, recv: [
  north_inport: {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},
  south_inport: {'payload': Bits64(0x0000000000000000), 'predicate': Bits1(0x0), 'bypass': Bits1(0x0), 'delay': Bits1(0x0)},

• Instead of recv_opt_msg: {'ctrl': Bits6(0x03), can we make it recv_ctrl_msg: {'opt': (++), Bits6(0x03) by using
  https://github.com/tancheng/VectorCGRA/blob/6b65a2c23ee83c3102b49ae0fd5343dc32ea5d47/lib/opt_type.py#L74C1-L74C16

[yyan7223]

Honestly, I don't get the point why we need to print those traces in such a fine-grained way. It exhibits too many details for users to identify which are useful. Maybe we should start with discussing the purpose of printing traces and then decide how we print it?

• If it is for checking whether the timing of our design is correct, the traditional Verilator+GTKWave might be more straightforward and reliable.
• If it is simply for demonstrating the dataflow among tiles, we can print those traces in a coarse-grained way. For example, the multiplication result of Tile0 at Cycle1 is routed to Tile2 at Cycle3 for adding:
  Cycle1: Tile0_Ch8&Ch9_Out -> Tile0_Fu(MUL) -> Tile0_Xbar -> Tile0_Ch2_Bypass -> Tile1_Xbar -> Tile1_Ch4_In
Cycle2: Tile1_Ch4_Out -> Tile2_Xbar -> Tile2_Ch8_In
Cycle3: Tile2_Ch8_Out -> Tile2_Fu(Add) -> Tile2_Xbar ->...

[tancheng]

Hi @yyan7223, thanks for the comments.

• We still want a pymtl level simulation trace dumped to debug without Verilator+GTKWave. Not everyone wanna dive into verilog.
• I agree on this. We can have two mode: verbose = 1 (default) & verbose = 2.

@yuqisun WDYT?

[tancheng]

You wanna create a new PR for this issue?

[yuqisun]

Will re-raise PR as I forked from tancheng/VectorCGRA now, as there's always a merge information in git log from coredac repo after it sync from tancheng.
Once merged to tancheng repo, I will sync in coredac then. Want to keep to use same parent repo with you.