Simulation traces are not understandable for human being #23

cgra/CGRAKingMeshRTL.py

@@ -155,5 +155,5 @@ def line_trace( s ):
     # str += " :: [" + s.data_mem.line_trace() + "]"
     res = "||\n".join([ (("[tile"+str(i)+"]: ") + x.line_trace() + x.ctrl_mem.line_trace())
                               for (i,x) in enumerate(s.tile) ])
-    res += "\n :: [" + s.data_mem.line_trace() + "]    \n"
+    res += "\n data_mem:: [" + s.data_mem.line_trace() + "]    \n"
     return res

cgra/translate/CGRATemplateRTL_test.py

@@ -187,8 +187,8 @@ def test_cgra_universal( cmdline_opts, paramCGRA = None):
   DUT               = CGRATemplateRTL
   FunctionUnit      = FlexibleFuRTL
   # FuList            = [ SeqMulAdderRTL, MemUnitRTL ]#AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL ]
-  # FuList           = [ PhiRTL, AdderRTL, ShifterRTL, MemUnitRTL, SelRTL, CompRTL, SeqMulAdderRTL, RetRTL, MulRTL, LogicRTL, BranchRTL ]
-  FuList           = [ PhiRTL, AdderRTL, ShifterRTL, MemUnitRTL, SelRTL, CompRTL, SeqMulAdderRTL, MulRTL, LogicRTL, BranchRTL ]
+  FuList           = [ PhiRTL, AdderRTL, ShifterRTL, MemUnitRTL, SelRTL, CompRTL, SeqMulAdderRTL, RetRTL, MulRTL, LogicRTL, BranchRTL ]
+  # FuList           = [ PhiRTL, AdderRTL, ShifterRTL, MemUnitRTL, SelRTL, CompRTL, SeqMulAdderRTL, MulRTL, LogicRTL, BranchRTL ]
   DataType          = mk_data( 32, 1 )
   PredicateType     = mk_predicate( 1, 1 )
 #  DataType         = mk_data( 16, 1 )
@@ -364,6 +364,7 @@ def handleReshape( t_tiles ):
   th = config_model_with_cmdline_opts( th, cmdline_opts, duts=['dut'] )
 
   if paramCGRA != None:
+    print(f'paramCGRA: {paramCGRA}')
     for tile in tiles:
         if not tile.isDefaultFus():
             targetFuList = []

fu/flexible/FlexibleFuRTL.py

@@ -8,6 +8,7 @@
   Date : Dec 24, 2019
 
 """
+import json
 
 from pymtl3 import *
 from ...fu.single.MemUnitRTL import MemUnitRTL
@@ -111,11 +112,12 @@ def comb_logic():
           s.fu_recv_in_rdy_vector[port][i] @= s.fu[i].recv_in[port].rdy
         s.recv_in[port].rdy @= reduce_or( s.fu_recv_in_rdy_vector[port] )
 
+
   def line_trace( s ):
     opt_str = " #"
     if s.recv_opt.en:
       opt_str = OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl]
-    out_str = ",".join([str(x.msg) for x in s.send_out])
-    recv_str = ",".join([str(x.msg) for x in s.recv_in])
-    return f'[recv: {recv_str}] {opt_str}(P{s.recv_opt.msg.predicate}) (const: {s.recv_const.msg}, en: {s.recv_const.en}) ] = [out: {out_str}] (recv_opt.rdy: {s.recv_opt.rdy}, recv_in[0].rdy: {s.recv_in[0].rdy}, recv_in[1].rdy: {s.recv_in[1].rdy}, recv_predicate.msg: {s.recv_predicate.msg}, {OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl]}, recv_opt.en: {s.recv_opt.en}, send[0].en: {s.send_out[0].en}) '
+    out_str = f'[{",".join([str(x.msg.__dict__) for x in s.send_out])}]'
+    recv_str = f'[{",".join([str(x.msg.__dict__) for x in s.recv_in])}]'
+    return f'class: {s.__class__.__name__}, [recv: {recv_str}] opt: {opt_str} (P{s.recv_opt.msg.predicate}) (const: {str(s.recv_const.msg.__dict__)}, en: {s.recv_const.en}) ] = [out: {out_str}] (recv_opt.rdy: {s.recv_opt.rdy}, recv_in[0].rdy: {s.recv_in[0].rdy}, recv_in[1].rdy: {s.recv_in[1].rdy}, recv_predicate.msg: {str(s.recv_predicate.msg.__dict__)}, {OPT_SYMBOL_DICT[s.recv_opt.msg.ctrl]}, recv_opt.en: {s.recv_opt.en}, send[0].en: {s.send_out[0].en}) '
 

fu/single/RetRTL.py

@@ -61,7 +61,8 @@ def comb_logic():
 
       if s.recv_opt.msg.ctrl == OPT_RET:
         # Branch is only used to set predication rather than delivering value.
-        s.send_out[0].msg @= DataType(s.recv_in[s.in0_idx].msg.payload, b1( 0 ), b1( 0 ) )
+        #                             payload,                          predicate, bypass,  delay
+        s.send_out[0].msg @= DataType(s.recv_in[s.in0_idx].msg.payload, b1( 0 ),   b1( 0 ), b1( 0 ) )
         if s.recv_in[s.in0_idx].msg.predicate == b1( 0 ):#s.const_zero.payload:
           s.send_out_predicate @= 0
         else:

mem/ctrl/CtrlMemRTL.py

@@ -73,6 +73,6 @@ def update_raddr():
             s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
 
   def line_trace( s ):
-    out_str  = "||".join([ str(data) for data in s.reg_file.regs ])
-    return f'{s.recv_ctrl.msg} : [{out_str}] : {s.send_ctrl.msg}'
+    out_str  = f'[{", ".join([ str(data.__dict__) for data in s.reg_file.regs ])}]'
+    return f'class: {s.__class__.__name__}, recv_ctrl_msg: {s.recv_ctrl.msg.__dict__} : out: {out_str} : send_ctrl_msg: {str(s.send_ctrl.msg.__dict__)}'
 

mem/data/DataMemRTL.py

@@ -99,12 +99,12 @@ def update_signal():
         s.recv_wdata[i].rdy @= Bits1( 1 )
 
   def line_trace(s):
-    recv_raddr_str = "recv_read_addr: " + "|".join([str(data.msg) for data in s.recv_raddr])
-    recv_waddr_str = "recv_write_addr: " + "|".join([str(data.msg) for data in s.recv_waddr])
-    recv_wdata_str = "recv_write_data: " + "|".join([str(data.msg) for data in s.recv_wdata])
-    content_str = "content: " + "|".join([str(data) for data in s.reg_file.regs])
-    send_rdata_str = "send_read_data: " + "|".join([str(data.msg) for data in s.send_rdata])
-    return f'{recv_raddr_str} || {recv_waddr_str} || {recv_wdata_str} || [{content_str}] || {send_rdata_str}'
+    recv_raddr_str = "recv_read_addr: " + f'[{", ".join([str(data.msg) for data in s.recv_raddr])}]'
+    recv_waddr_str = "recv_write_addr: " + f'[{", ".join([str(data.msg) for data in s.recv_waddr])}]'
+    recv_wdata_str = "recv_write_data: " + f'[{", ".join([str(data.msg.__dict__) for data in s.recv_wdata])}]'
+    content_str = "content: " + f'[{", ".join([str(data.__dict__) for data in s.reg_file.regs])}]'
+    send_rdata_str = "send_read_data: " + f'[{", ".join([str(data.msg) for data in s.send_rdata])}]'
+    return f'class: {s.__class__.__name__}, {recv_raddr_str} || {recv_waddr_str} || {recv_wdata_str} || [{content_str}] || {send_rdata_str}'
     # return f'DataMem: {recv_str} : [{out_str}] : {send_str} initWrites: {s.initWrites}'
     # return s.reg_file.line_trace()
     # return f'<{s.reg_file.wen[0]}>{s.reg_file.waddr[0]}:{s.reg_file.wdata[0]}|{s.reg_file.raddr[0]}:{s.reg_file.rdata[0]}'

tile/TileRTL.py

@@ -6,6 +6,7 @@
 Author : Cheng Tan
   Date : Dec 11, 2019
 """
+import json
 
 
 from pymtl3 import *
@@ -123,12 +124,13 @@ def update_opt():
       s.crossbar.recv_opt.en   @= s.ctrl_mem.send_ctrl.en
       s.ctrl_mem.send_ctrl.rdy @= s.element.recv_opt.rdy & s.crossbar.recv_opt.rdy
 
+
   # Line trace
   def line_trace( s ):
-
-    recv_str    = "|".join([ str(x.msg) for x in s.recv_data ])
-    channel_recv_str = "|".join([ str(x.recv.msg) for x in s.channel ])
-    channel_send_str = "|".join([ str(x.send.msg) for x in s.channel ])
-    out_str  = "|".join([ "("+str(x.msg.payload)+","+str(x.msg.predicate)+")" for x in s.send_data ])
-    return f"{recv_str} => [{s.crossbar.recv_opt.msg}] ({s.element.line_trace()}) => {channel_recv_str} => {channel_send_str} => {out_str}"
+    recv_str    = f'[{", ".join([ str(x.msg.__dict__) for x in s.recv_data ])}]'
+    # recv_json = json.dumps(s.recv_data)
+    channel_recv_str = f'[{", ".join([ str(x.recv.msg.__dict__) for x in s.channel ])}]'
+    channel_send_str = f'[{", ".join([ str(x.send.msg.__dict__) for x in s.channel ])}]'
+    out_str  = f'[{", ".join([ "{send_msg_payload: "+str(x.msg.payload)+", send_msg_predicate: "+str(x.msg.predicate)+"}" for x in s.send_data ])}]'
+    return f"class: {s.__class__.__name__}, recv: {recv_str} => [recv_opt_msg: {str(s.crossbar.recv_opt.msg.__dict__)}] ({s.element.line_trace()}) => channel_recv: {channel_recv_str} => channel_send: {channel_send_str} => out: {out_str}"