Code

Crossbar based data SRAM#40

Code

Merged

tancheng merged 17 commits intomastertancheng/VectorCGRA:masterfrom data_mem_xbartancheng/VectorCGRA:data_mem_xbarCopy head branch name to clipboardDec 18, 2024

+1,289-738

Commits

Commits on Dec 7, 2024

• [feature] Initialize test for variations of DataMemRTL

  tancheng

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  2f7964e

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Commits on Dec 13, 2024

• [feature] Xbar based DataSram with support of remote access

  tancheng

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  2ec70c4

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• [fix] Tests with new pkt type

  tancheng

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  8e592d2

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• [fix] Tests with NoC pkt, including cmd/addr

  tancheng

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  73c0cbd

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• [fix] Pkt types

  tancheng

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  143026a

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• [fix] Pkt type for translation

  tancheng

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  ea40dc3

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Commits on Dec 14, 2024

• [feature] Enable data memory with crossbar be translatable

  tancheng

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  48665c0

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Commits on Dec 16, 2024

• [feature] Refactors the controller to make it be connectable with data memory with crossbar

  tancheng

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  48d29c1

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Commits on Dec 17, 2024

• [feature] Enables simulation for CGRA with crossbar-based memory

  tancheng

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  fb53b63

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• [feature] Enables simulation (not verification) for ring-based multi-cgra

  tancheng

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  aff5ec4

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• [feature] Includes CGRAWithCrossbarDataMemRTL

  tancheng

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  db9ce90

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• [feature] Enables translation of CGRAWithCrossbarDataMemRTL with LUT for global addr2controller

  tancheng

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  69356a3

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• [feature] Adds tests in github actions

  tancheng

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  5b45d85

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• [fix] Removes unnecessary CGRAWithControllerRTL test (too many ifcs/wires between SRAM and controller, so give up modeling it, instead, we already provide CGRA containing SRAM and controller)

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  14a247b

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• [fix] translation failure due to trunc

  tancheng

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  6f969db

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• [fix] Includes CGRAWithCrossbarDataMemRTL_test for translation

  tancheng

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  51d3f90

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Commits on Dec 18, 2024

• [feature] Not using temp variables to avoid potential non-unrollable for loop in synthesis

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  3542cbc

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