Crossbar based data SRAM

[tancheng]

A crossbar is in between the data memory and the tiles.

• Allows the crossbar to send requests to NoC (via controller).
  • For now, the outstanding request would block all the other remote access requests.
• Need to check the generated/translated SVerilog.

       for i in range(num_xbar_in_rd_ports):
         arbitrated_rd_msg = s.read_crossbar.packet_on_input_units[i]
         if (s.read_crossbar.send[arbitrated_rd_msg.dst].msg.src == i) & (arbitrated_rd_msg.dst < num_banks):
           loaded_msg = s.reg_file[trunc(arbitrated_rd_msg.dst, LocalBankIndexType)].rdata[0]
           if i <= s.num_rd_tiles:

• Not sure how synthesizer would handle this, replacing temporary variables with original ones for now.
• E2e test
  • Global address space needs to be partitioned across distributed SRAM banks.
  • Larger test, i.e., multi-CGRA with controller and crossbar-based data memories.
    • Checks whether the remote request can get correct response. Can be done in another PR @yuqisun, [P1] Provide e2e simulation/verification for ring-multi-cgra #44.
• Different types of requests/messages:
  • Memory access pkt go through the xbar.
  • Load/store requests on NoC.
  • Commands go through NoC.

TODO in next PRs:

• Blocking and non-blocking ability (through configuration), [P1] Data arrival-dependent execution and cycle-based execution #26.

[yuqisun]

Cool!